| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixed SRAM routing logic | Mike Stirling | 2011-07-16 | 1 | -8/+8 |
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| * | Added top-level, PLL, MOS ROM and CRTC. CRTC seems to behave strangely ↵ | Mike Stirling | 2011-07-16 | 1 | -0/+365 |
| although the design is passing timing. | |||||
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index : bbc-b/fpga-bbc | |
| bbc-b fpga implementation from GH | James |
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