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author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-30 10:39:52 +0100 |
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committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-30 10:39:52 +0100 |
commit | fc9ea65b8ac1849c9756cc58e6f14500646b1d8c (patch) | |
tree | 7a520dc724130cda33537f79b01fe3129f6bd9c0 /m6522.vhd | |
parent | 22139faee8f39c1a2d5e03f35d586fcf3eda472b (diff) | |
download | fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.tar.gz fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.tar.bz2 fpga-bbc-fc9ea65b8ac1849c9756cc58e6f14500646b1d8c.zip |
Keyboard now working (needed to loop back slow bus outputs to inputs on system VIA). Added aux input to debugger for display of arbitrary hex values. Removed test IFR output from 6522
Diffstat (limited to 'm6522.vhd')
-rw-r--r-- | m6522.vhd | 5 |
1 files changed, 1 insertions, 4 deletions
@@ -90,8 +90,7 @@ entity M6522 is I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
- CLK : in std_logic;
- testout : out std_logic_vector(7 downto 0)
+ CLK : in std_logic
);
end;
@@ -192,8 +191,6 @@ architecture RTL of M6522 is signal final_irq : std_logic;
begin
- testout <= r_ifr and "1" & r_ier;
-
p_phase : process
begin
-- internal clock phase
|