Keyboard now working (needed to loop back slow bus outputs to inputs on system VIA). Added aux input to debugger for display of arbitrary hex values. Removed test IFR output from 6522

5 files changed, 66 insertions, 40 deletions

diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index 3e53add..a32d934 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -310,8 +310,7 @@ component M6522 is
     I_P2_H            : in    std_logic; -- high for phase 2 clock  ____----__

     RESET_L           : in    std_logic;

     ENA_4             : in    std_logic; -- clk enable (4x system clock rate)

-    CLK               : in    std_logic;

-    testout : out std_logic_vector(7 downto 0)

+    CLK               : in    std_logic

     );

 end component;

 

@@ -361,12 +360,19 @@ port (
 	CLKEN_IN	:	in	std_logic;

 	-- Gated clock enable back out to CPU

 	CLKEN_OUT	:	out	std_logic;

+	-- CPU IRQ in

+	nIRQ_IN		:	in	std_logic;

+	-- Gated IRQ back out to CPU (no interrupts when single stepping)

+	nIRQ_OUT	:	out	std_logic;

 	

 	-- CPU

 	A_CPU		:	in	std_logic_vector(15 downto 0);

 	R_nW		:	in	std_logic;

 	SYNC		:	in	std_logic;

 	

+	-- Aux bus input for display in hex

+	AUX_BUS		:	in	std_logic_vector(15 downto 0);	

+	

 	-- Controls

 	-- RUN or HALT CPU

 	RUN			:	in	std_logic;

@@ -418,6 +424,10 @@ signal mhz1_clken		:	std_logic; -- 1 MHz bus and associated peripherals, 6522 ph
 -- Testing

 signal test_uart_do		:	std_logic_vector(7 downto 0);

 

+-- Debugger connections

+signal debug_irq_in_n	:	std_logic;

+signal debug_aux		:	std_logic_vector(15 downto 0);

+

 -- CPU signals

 signal cpu_mode			:	std_logic_vector(1 downto 0);

 signal cpu_ready		:	std_logic;

@@ -485,7 +495,6 @@ signal sys_via_cb2_oe_n	:	std_logic;
 signal sys_via_pb_in	:	std_logic_vector(7 downto 0);

 signal sys_via_pb_out	:	std_logic_vector(7 downto 0);

 signal sys_via_pb_oe_n	:	std_logic_vector(7 downto 0);

-signal sys_via_testout	:	std_logic_vector(7 downto 0);

 

 -- User VIA signals

 signal user_via_do		:	std_logic_vector(7 downto 0);

@@ -507,7 +516,6 @@ signal user_via_cb2_oe_n	:	std_logic;
 signal user_via_pb_in	:	std_logic_vector(7 downto 0);

 signal user_via_pb_out	:	std_logic_vector(7 downto 0);

 signal user_via_pb_oe_n	:	std_logic_vector(7 downto 0);

-signal user_via_testout	:	std_logic_vector(7 downto 0);

 

 -- IC32 latch on System VIA

 signal ic32				:	std_logic_vector(7 downto 0);

@@ -570,7 +578,10 @@ begin
 		hard_reset_n,

 		cpu_clken,

 		cpu_debug_clken,

+		debug_irq_in_n,

+		cpu_irq_n,

 		cpu_a(15 downto 0), cpu_r_nw, cpu_sync,

+		debug_aux,

 		SW(8), -- RUN

 		KEY(3), -- STEP

 		KEY(2), -- MODE

@@ -689,7 +700,7 @@ begin
 		mhz1_clken,

 		hard_reset_n, -- System VIA is reset by power on reset only

 		mhz4_clken,

-		clock, sys_via_testout

+		clock

 		);

 	

 	-- User VIA

@@ -721,7 +732,7 @@ begin
 		mhz1_clken,

 		reset_n,

 		mhz4_clken,

-		clock, user_via_testout

+		clock

 		);

 		

 	-- Keyboard

@@ -887,8 +898,8 @@ begin
 		user_via_do	when user_via_enable = '1' else

 		test_uart_do when io_fred = '1' else

 		(others => '0'); -- un-decoded locations are pulled down by RP1

-	cpu_irq_n <= sys_via_irq_n; -- and user_via_irq_n;

-	--cpu_irq_n <= '1';

+	debug_irq_in_n <= sys_via_irq_n and user_via_irq_n; -- route IRQ through debugger

+	--cpu_irq_n <= sys_via_irq_n and user_via_irq_n;

 	

 	-- ROMs are in external flash

 	FL_RST_N <= reset_n;

@@ -900,10 +911,9 @@ begin
 	FL_ADDR(15 downto 14) <= 

 		"00" when mos_enable = '1' else

 		"01" when rom_enable = '1' and romsel(1 downto 0) = "11" else	-- BASIC

-		--"10" when rom_enable = '1' and romsel(1 downto 0) = "00" else

+		"10" when rom_enable = '1' and romsel(1 downto 0) = "00" else	-- DFS

 		"11";

 		

-	

 	-- SRAM bus

 	SRAM_UB_N <= '1';

 	SRAM_LB_N <= '0';

@@ -983,11 +993,6 @@ begin
 	g_in <= '0';

 	b_in <= '0';

 	

-	GPIO_0(0) <= cpu_irq_n;

-	GPIO_0(1) <= keyb_out;

-	GPIO_0(2) <= keyb_enable_n;

-	GPIO_0(3) <= sys_via_testout(6); -- timer 1

-	

 	-- CRTC drives video out (CSYNC on HSYNC output, VSYNC high)

 	VGA_HS <= not (crtc_hsync xor crtc_vsync);

 	VGA_VS <= '1';

@@ -1004,15 +1009,15 @@ begin
 	-- Keyboard

 	sys_via_ca2_in <= keyb_int;

 	sys_via_pa_in(7) <= keyb_out;

+	sys_via_pa_in(6 downto 0) <= sys_via_pa_out(6 downto 0); -- Must loop back output pins or keyboard won't work

 	keyb_column <= sys_via_pa_out(3 downto 0);

 	keyb_row <= sys_via_pa_out(6 downto 4);

 	-- Others (idle until missing bits implemented)

-	sys_via_pa_in(6 downto 0) <= (others => '0');

 	sys_via_pb_in(7 downto 4) <= (others => '1');

 	

 	-- Connections to User VIA (user port is output on green LEDs)

-	--LEDG <= user_via_pb_out;

-	LEDG <= sys_via_testout;

+	user_via_ca1_in <= '1'; -- Pulled up

+	LEDG <= user_via_pb_out;

 	

 	-- ROM select latch

 	process(clock,reset_n)

@@ -1050,5 +1055,13 @@ begin
 	-- Keyboard LEDs

 	LEDR(0) <= not caps_lock_led_n;

 	LEDR(1) <= not shift_lock_led_n;

+	

+	-----------------

+	-- DEBUG STUFF

+	-----------------

+	

+	GPIO_0(0) <= cpu_irq_n;

+	GPIO_0(1) <= keyb_out;

+	GPIO_0(2) <= keyb_enable_n;

 

 end architecture;

diff --git a/debugger.vhd b/debugger.vhd
index bf82850..9d842e2 100644
--- a/debugger.vhd
+++ b/debugger.vhd
@@ -21,12 +21,19 @@ port (
 	CLKEN_IN	:	in	std_logic;

 	-- Gated clock enable back out to CPU

 	CLKEN_OUT	:	out	std_logic;

+	-- CPU IRQ in

+	nIRQ_IN		:	in	std_logic;

+	-- Gated IRQ back out to CPU (no interrupts when single stepping)

+	nIRQ_OUT	:	out	std_logic;

 	

 	-- CPU

 	A_CPU		:	in	std_logic_vector(15 downto 0);

 	R_nW		:	in	std_logic;

 	SYNC		:	in	std_logic;

 	

+	-- Aux bus input for display in hex

+	AUX_BUS		:	in	std_logic_vector(15 downto 0);

+	

 	-- Controls

 	-- RUN or HALT CPU

 	RUN			:	in	std_logic;

@@ -60,7 +67,7 @@ port (
 end component;

 

 -- Current display mode

-type mode_t is (modeAddress,modeBreak,modeWatch);

+type mode_t is (modeAddress,modeBreak,modeWatch,modeAux);

 signal mode			:	mode_t;

 -- Current edit digit

 signal digit		:	unsigned(1 downto 0);

@@ -95,11 +102,14 @@ signal r_set_n		:	std_logic;
 begin

 	-- Mask CPU clock enable

 	CLKEN_OUT <= CLKEN_IN and not halt;

+	-- Mask interrupt

+	nIRQ_OUT <= nIRQ_IN or not RUN;

 	

 	-- Route selected address to display

 	a_display <= instr_addr when mode = modeAddress else

 		breakpoint when mode = modeBreak else

 		watchpoint when mode = modeWatch else

+		AUX_BUS when mode = modeAux else

 		(others => '0');

 

 	-- Generate display digits from binary

@@ -109,14 +119,14 @@ begin
 	d0 : seg7 port map (a_display(3 downto 0),d0_display);

 	

 	-- Flash selected digit in edit modes

-	DIGIT3 <= d3_display when (mode = modeAddress or flash = '1' or digit /= "11") else "1111111";

-	DIGIT2 <= d2_display when (mode = modeAddress or flash = '1' or digit /= "10") else "1111111";

-	DIGIT1 <= d1_display when (mode = modeAddress or flash = '1' or digit /= "01") else "1111111";

-	DIGIT0 <= d0_display when (mode = modeAddress or flash = '1' or digit /= "00") else "1111111";

+	DIGIT3 <= d3_display when (mode = modeAddress or mode = modeAux or flash = '1' or digit /= "11") else "1111111";

+	DIGIT2 <= d2_display when (mode = modeAddress or mode = modeAux or flash = '1' or digit /= "10") else "1111111";

+	DIGIT1 <= d1_display when (mode = modeAddress or mode = modeAux or flash = '1' or digit /= "01") else "1111111";

+	DIGIT0 <= d0_display when (mode = modeAddress or mode = modeAux or flash = '1' or digit /= "00") else "1111111";

 	

 	-- Show mode on LEDs

-	LED_BREAKPOINT <= '1' when mode = modeBreak else '0';

-	LED_WATCHPOINT <= '1' when mode = modeWatch else '0';

+	LED_BREAKPOINT <= '1' when mode = modeBreak or mode = modeAux else '0';

+	LED_WATCHPOINT <= '1' when mode = modeWatch or mode = modeAux else '0';

 

 	-- Flash counter

 	process(CLOCK,nRESET)

@@ -153,6 +163,8 @@ begin
 					mode <= modeBreak;

 				elsif mode = modeBreak then

 					mode <= modeWatch;

+				elsif mode = modeWatch then

+					mode <= modeAux;

 				else

 					mode <= modeAddress;

 				end if;

@@ -215,6 +227,11 @@ begin
 			-- Register single-step button

 			r_step_n <= nSTEP;

 			

+			-- Once the CPU has run we can trigger a new halt

+			if CLKEN_IN = '1' then

+				resuming <= '0';

+			end if;

+			

 			if SYNC = '1' then

 				-- Latch address of instruction fetch

 				instr_addr <= A_CPU;

@@ -242,11 +259,6 @@ begin
 				resuming <= '1';

 				halt <= '0';

 			end if;

-			

-			-- Once the CPU has run we can trigger a new halt

-			if CLKEN_IN = '1' then

-				resuming <= '0';

-			end if;

 		end if;

 	end process;

 end architecture;

diff --git a/keyboard.vhd b/keyboard.vhd
index 0558469..2c874f3 100644
--- a/keyboard.vhd
+++ b/keyboard.vhd
@@ -63,7 +63,7 @@ signal keyb_valid	:	std_logic;
 signal keyb_error	:	std_logic;

 

 -- Internal signals

-type key_matrix is array(0 to 9) of std_logic_vector(7 downto 0);

+type key_matrix is array(0 to 15) of std_logic_vector(7 downto 0);

 signal keys			:	key_matrix;

 signal col			:	unsigned(3 downto 0);

 signal release		:	std_logic;

@@ -133,6 +133,13 @@ begin
 			keys(7) <= (others => '0');

 			keys(8) <= (others => '0');

 			keys(9) <= (others => '0');

+			-- These non-existent rows are used in the BBC master

+			keys(10) <= (others => '0');

+			keys(11) <= (others => '0');

+			keys(12) <= (others => '0');

+			keys(13) <= (others => '0');

+			keys(14) <= (others => '0');

+			keys(15) <= (others => '0');

 		elsif rising_edge(CLOCK) then

 			-- Copy DIP switches through to row 0

 			keys(2)(0) <= DIP_SWITCH(7);

diff --git a/m6522.vhd b/m6522.vhd
index a0dd241..fe82b3f 100644
--- a/m6522.vhd
+++ b/m6522.vhd
@@ -90,8 +90,7 @@ entity M6522 is
     I_P2_H            : in    std_logic; -- high for phase 2 clock  ____----__

     RESET_L           : in    std_logic;

     ENA_4             : in    std_logic; -- clk enable

-    CLK               : in    std_logic;

-    testout : out std_logic_vector(7 downto 0)

+    CLK               : in    std_logic

     );

 end;

 

@@ -192,8 +191,6 @@ architecture RTL of M6522 is
 

   signal final_irq         : std_logic;

 begin

-	testout <= r_ifr and "1" & r_ier;

-

   p_phase : process

   begin

     -- internal clock phase

diff --git a/m6522_tb.vhd b/m6522_tb.vhd
index eb76db5..023eb2e 100644
--- a/m6522_tb.vhd
+++ b/m6522_tb.vhd
@@ -46,8 +46,7 @@ component M6522 is
     I_P2_H            : in    std_logic; -- high for phase 2 clock  ____----__

     RESET_L           : in    std_logic;

     ENA_4             : in    std_logic; -- clk enable

-    CLK               : in    std_logic;

-    testout		: out std_logic_vector(7 downto 0)

+    CLK               : in    std_logic

     );

 end component;

 

@@ -81,8 +80,6 @@ signal n_reset	:	std_logic := '0';
 signal clken	:	std_logic := '0';

 signal clock	:	std_logic := '0';

 

-signal testout : std_logic_vector(7 downto 0);

-

 begin

 

 	uut: m6522 port map (

@@ -93,7 +90,7 @@ begin
 		cb1_in, cb1_out, n_cb1_oe,

 		cb2_in, cb2_out, n_cb2_oe,

 		pb_in, pb_out, n_pb_oe,

-		phase2, n_reset, clken, clock, testout

+		phase2, n_reset, clken, clock

 		);

 		

 	clock <= not clock after 125 ns; -- 4x 1 MHz