diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx')
-rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.c | 23 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.h | 8 |
2 files changed, 16 insertions, 15 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 84e27a251..adc645832 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -128,22 +128,16 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED)
dmaInit();
+#endif
-#if 0 /*defined(STM32F7XX)*/
- /* If the DMA is in use then the DMA-accessible RAM must be programmed as
- Write Through using the MPU, region zero is used with a size of 512kB,
- the sub-regions are programmed as follow:
- - 0,, disabled, it is the normal the DTCM RAM.
- - 1..4, enabled, it is the normal, DMA-accessible, RAM.
- - 5..7, disabled, beyond RAM area.
- The system memory layout is used as "background" for the MPU regions.*/
- mpuConfigureRegion(MPU_REGION_0,
- 0x20000000U,
+#if STM32_SRAM2_NOCACHE
+ /* The SRAM2 bank can optionally made a non cache-able area for use by
+ DMA engines.*/
+ mpuConfigureRegion(MPU_REGION_7,
+ 0x2004C000U,
MPU_RASR_ATTR_AP_RW_RW |
- MPU_RASR_ATTR_CACHEABLE_WT_NWA |
- MPU_RASR_SRD_DISABLE_SUB0 | MPU_RASR_SRD_DISABLE_SUB5 |
- MPU_RASR_SRD_DISABLE_SUB6 | MPU_RASR_SRD_DISABLE_SUB7 |
- MPU_RASR_SIZE_512K |
+ MPU_RASR_ATTR_NON_CACHEABLE |
+ MPU_RASR_SIZE_16K |
MPU_RASR_ENABLE);
mpuEnable(MPU_CTRL_PRIVDEFENA);
@@ -151,7 +145,6 @@ void hal_lld_init(void) { immediately.*/
SCB_CleanInvalidateDCache();
#endif
-#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 5645e0bc9..dcd5beadd 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -822,6 +822,14 @@ #if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#endif
+
+/**
+ * @brief SRAM2 cache-ability.
+ * @note This setting uses the MPU region 7 if at @p TRUE.
+ */
+#if !defined(STM32_SRAM2_NOCACHE) || defined(__DOXYGEN__)
+#define STM32_SRAM2_NOCACHE FALSE
+#endif
/** @} */
/*===========================================================================*/
|