diff options
| -rw-r--r-- | demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h | 1 | ||||
| -rw-r--r-- | os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld | 7 | ||||
| -rw-r--r-- | os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld | 7 | ||||
| -rw-r--r-- | os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld | 31 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.c | 23 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.h | 8 |
6 files changed, 46 insertions, 31 deletions
diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h index cf2417809..e9b5b8ab7 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h @@ -88,6 +88,7 @@ #define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
+#define STM32_SRAM2_NOCACHE FALSE
/*
* ADC driver system settings.
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld index f955bd899..81fb0fb89 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld @@ -49,7 +49,10 @@ REGION_ALIAS("DATA_RAM", ram0); /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for DMA segment.*/
-REGION_ALIAS("DMA_RAM", ram0);
+/* RAM region to be used for NOCACHE segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for ETH segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
INCLUDE ld/rules_STM32F7xx.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld index 7abc1787e..a8e0626d2 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld @@ -48,7 +48,10 @@ REGION_ALIAS("DATA_RAM", ram1); /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1);
-/* RAM region to be used for DMA segment.*/
-REGION_ALIAS("DMA_RAM", ram2);
+/* RAM region to be used for NOCACHE segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for ETH segment.*/
+REGION_ALIAS("ETH_RAM", ram2);
INCLUDE rules_dma.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld index 93ed8af3a..39aad4419 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld @@ -109,20 +109,27 @@ SECTIONS _etext = .;
_textdata = _etext;
- /* Special section for DMA-accessible areas, it is desirable to have a
- separate section of DMA-accessible areas for several reasons:
- - On devices with cache, the whole region can be declared not cacheable
- removing issues with cache consistency.
- - DMA-accessible areas can be placed on a dedicated SRAM bank for
- improved concurrent accesses.*/
- .dma (NOLOAD) : ALIGN(4)
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
{
- *(.dma)
- *(.dma.*)
- *(.bss.__dma_*)
+ __nocache_start__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
. = ALIGN(4);
- __dma_free__ = .;
- } > DMA_RAM
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .ethram (NOLOAD) : ALIGN(4)
+ {
+ __ethram_start__ = .;
+ *(.ethram)
+ *(.ethram.*)
+ *(.bss.__ethram_*)
+ . = ALIGN(4);
+ __ethram_end__ = .;
+ } > ETH_RAM
.mstack :
{
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 84e27a251..adc645832 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -128,22 +128,16 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED)
dmaInit();
+#endif
-#if 0 /*defined(STM32F7XX)*/
- /* If the DMA is in use then the DMA-accessible RAM must be programmed as
- Write Through using the MPU, region zero is used with a size of 512kB,
- the sub-regions are programmed as follow:
- - 0,, disabled, it is the normal the DTCM RAM.
- - 1..4, enabled, it is the normal, DMA-accessible, RAM.
- - 5..7, disabled, beyond RAM area.
- The system memory layout is used as "background" for the MPU regions.*/
- mpuConfigureRegion(MPU_REGION_0,
- 0x20000000U,
+#if STM32_SRAM2_NOCACHE
+ /* The SRAM2 bank can optionally made a non cache-able area for use by
+ DMA engines.*/
+ mpuConfigureRegion(MPU_REGION_7,
+ 0x2004C000U,
MPU_RASR_ATTR_AP_RW_RW |
- MPU_RASR_ATTR_CACHEABLE_WT_NWA |
- MPU_RASR_SRD_DISABLE_SUB0 | MPU_RASR_SRD_DISABLE_SUB5 |
- MPU_RASR_SRD_DISABLE_SUB6 | MPU_RASR_SRD_DISABLE_SUB7 |
- MPU_RASR_SIZE_512K |
+ MPU_RASR_ATTR_NON_CACHEABLE |
+ MPU_RASR_SIZE_16K |
MPU_RASR_ENABLE);
mpuEnable(MPU_CTRL_PRIVDEFENA);
@@ -151,7 +145,6 @@ void hal_lld_init(void) { immediately.*/
SCB_CleanInvalidateDCache();
#endif
-#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 5645e0bc9..dcd5beadd 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -822,6 +822,14 @@ #if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#endif
+
+/**
+ * @brief SRAM2 cache-ability.
+ * @note This setting uses the MPU region 7 if at @p TRUE.
+ */
+#if !defined(STM32_SRAM2_NOCACHE) || defined(__DOXYGEN__)
+#define STM32_SRAM2_NOCACHE FALSE
+#endif
/** @} */
/*===========================================================================*/
|