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-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c6
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.h1
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c142
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.c835
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.h50
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sama5d2.h44
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.c258
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.h21
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/driver.mk4
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_conf.h3
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c6
-rw-r--r--os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.h12
-rw-r--r--os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h27
-rw-r--r--testhal/ATSAMA5D2/SDMMC/main.c15
-rw-r--r--testhal/ATSAMA5D2/SDMMC/mcuconf.h4
15 files changed, 72 insertions, 1356 deletions
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c
index aabf0d153..e8bf714ce 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c
@@ -98,7 +98,7 @@ void SdMmcUpdateInformation(SdmmcDriver *drv, bool csd, bool extData)
uint8_t SDMMC_Lib_SdStart(SdmmcDriver *drv, bool * retry)
{
uint64_t mem_size;
- //uint32_t freq;
+ uint32_t freq;
uint32_t drv_err, status;
uint8_t error;
bool flag;
@@ -272,7 +272,7 @@ uint8_t SDMMC_Lib_SdStart(SdmmcDriver *drv, bool * retry)
error = HwSetClock(drv, &freq);
drv->card.dwCurrSpeed = freq;
if (error != SDMMC_OK && error != SDMMC_CHANGED) {
- TRACE_ERROR_1("clk %s\n\r", SD_StringifyRetCode(error));
+ TRACE_ERROR_1("error clk %s\n\r", SD_StringifyRetCode(error));
return error;
}
#endif
@@ -286,7 +286,7 @@ uint8_t SDMMC_Lib_SdStart(SdmmcDriver *drv, bool * retry)
//warning
if (status) {
- TRACE_WARNING_1("st %lx\n\r", status);
+ TRACE_WARNING_1("warning st %lx\n\r", status);
}
return SDMMC_OK;
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.h b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.h
index f675996e4..29f1119da 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.h
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.h
@@ -164,7 +164,6 @@ typedef enum {
#define CARD_SDHCCOMBO (CARD_TYPE_bmSDIO|CARD_SDHC)
#include "ch_sdmmc_macros.h"
-#include "ch_sdmmc_pmc.h"
#include "ch_sdmmc_trace.h"
extern const uint16_t sdmmcTransUnits[8];
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c
index 9c1163d95..3f1ad6852 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c
@@ -6,8 +6,6 @@
#include "sama_sdmmc_lld.h"
#include "ch_sdmmc_device.h"
#include "ch_sdmmc_cmds.h"
-#include "ch_sdmmc_pmc.h"
-#include "ch_sdmmc_tc.h"
#include "ch_sdmmc_sdio.h"
#include "ch_sdmmc_sd.h"
#include "ch_sdmmc_mmc.h"
@@ -67,16 +65,8 @@ uint8_t sdmmc_device_lowlevelcfg(SdmmcDriver *driver)
uint8_t res;
- pmc_set_main_oscillator_freq(BOARD_MAIN_CLOCK_EXT_OSC);
-
- TRACE_INFO_1("Processor clock: %u MHz\r\n", ((unsigned)(pmc_get_processor_clock() / 1000000) ));
- TRACE_INFO_1("Master clock: %u MHz\r\n", ((unsigned)(pmc_get_master_clock() / 1000000)) );
-
-#if SDMMC_USE_TC == 1
- driver->tctimer_id = get_tc_id_from_addr(driver->config->tctimer,driver->config->tc_chan);
- pmc_configure_peripheral(driver->tctimer_id, NULL, true);
-#endif
-
+ TRACE_INFO_1("Processor clock: %u MHz\r\n", ((unsigned)(SAMA_PCK / 1000000) ));
+ TRACE_INFO_1("Master clock: %u MHz\r\n", ((unsigned)(SAMA_MCK / 1000000)) );
if (driver->config->slot_id == SDMMC_SLOT0) {
driver->regs = SDMMC0;
@@ -88,18 +78,6 @@ uint8_t sdmmc_device_lowlevelcfg(SdmmcDriver *driver)
;
}
- pmc_configure_peripheral((SDMMC_SLOT0 + driver->config->slot_id), NULL, true);
-
- if (driver->config->use_fastest_clock) {
-
- pmc_enable_upll_clock();
- pmc_enable_upll_bias();
- }
-
- pmc_configure_peripheral((SDMMC_SLOT0 + driver->config->slot_id),
- &driver->config->pmccfg, true);
-
-
switch (driver->config->slot_id) {
case SDMMC_SLOT0: {
@@ -112,31 +90,25 @@ uint8_t sdmmc_device_lowlevelcfg(SdmmcDriver *driver)
/* Configure SDMMC0 pins */
/** SDMMC0 pin Card Detect (CD) */
- //#define PIN_SDMMC0_CD_IOS1 { PIO_GROUP_A, PIO_PA13A_SDMMC0_CD, PIO_PERIPH_A, PIO_PULLUP }
- palSetGroupMode(PIOA, PIO_PA13A_SDMMC0_CD, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN13), 0U,
PAL_SAMA_FUNC_PERIPH_A | PAL_MODE_INPUT_PULLUP);
/** SDMMC0 pin Card Clock (CK) */
- //#define PIN_SDMMC0_CK_IOS1 { PIO_GROUP_A, PIO_PA0A_SDMMC0_CK, PIO_PERIPH_A, PIO_DEFAULT }
- palSetGroupMode(PIOA, PIO_PA0A_SDMMC0_CK, 0U, PAL_SAMA_FUNC_PERIPH_A);
+ palSetGroupMode(PIOA, (1u << 0), 0U, PAL_SAMA_FUNC_PERIPH_A);
/** SDMMC0 pin Card Command (CMD) */
- //#define PIN_SDMMC0_CMD_IOS1 { PIO_GROUP_A, PIO_PA1A_SDMMC0_CMD, PIO_PERIPH_A, PIO_PULLUP }
- palSetGroupMode(PIOA, PIO_PA1A_SDMMC0_CMD, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN1), 0U,
PAL_SAMA_FUNC_PERIPH_A | PAL_MODE_INPUT_PULLUP);
/** SDMMC0 pin Card Reset (RSTN) */
- //#define PIN_SDMMC0_RSTN_IOS1 { PIO_GROUP_A, PIO_PA10A_SDMMC0_RSTN, PIO_PERIPH_A, PIO_PULLUP }
- palSetGroupMode(PIOA, PIO_PA10A_SDMMC0_RSTN, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN10), 0U,
PAL_SAMA_FUNC_PERIPH_A | PAL_MODE_INPUT_PULLUP);
/** SDMMC0 pin VDD Selection (VDDSEL) */
- //#define PIN_SDMMC0_VDDSEL_IOS1 { PIO_GROUP_A, PIO_PA11A_SDMMC0_VDDSEL, PIO_PERIPH_A, PIO_DEFAULT }
- palSetGroupMode(PIOA, PIO_PA11A_SDMMC0_VDDSEL, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN11), 0U,
PAL_SAMA_FUNC_PERIPH_A);
/** SDMMC0 pin 8-bit Data (DA0-7) */
- //#define PINS_SDMMC0_DATA8B_IOS1 { PIO_GROUP_A, 0x000003fc, PIO_PERIPH_A, PIO_PULLUP }
palSetGroupMode(PIOA, 0x000003fc, 0U,
PAL_SAMA_FUNC_PERIPH_A | PAL_MODE_INPUT_PULLUP);
@@ -152,22 +124,18 @@ uint8_t sdmmc_device_lowlevelcfg(SdmmcDriver *driver)
sdmmc_set_capabilities(SDMMC1, caps0, CAPS0_MASK, 0, 0);
/* Configure SDMMC1 pins */
-
/** SDMMC1 pin Card Detect (CD) */
- palSetGroupMode(PIOA, PIO_PA30E_SDMMC1_CD, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN30), 0U,
PAL_SAMA_FUNC_PERIPH_E | PAL_MODE_INPUT_PULLUP);
/** SDMMC1 pin Card Clock (CK) */
- // #define PIN_SDMMC1_CK_IOS1 { PIO_GROUP_A, PIO_PA22E_SDMMC1_CK, PIO_PERIPH_E, PIO_DEFAULT }
- palSetGroupMode(PIOA, PIO_PA22E_SDMMC1_CK, 0U, PAL_SAMA_FUNC_PERIPH_E);
+ palSetGroupMode(PIOA, (1u << PIOA_PIN22), 0U, PAL_SAMA_FUNC_PERIPH_E);
/** SDMMC1 pin Card Command (CMD) */
- //#define PIN_SDMMC1_CMD_IOS1 { PIO_GROUP_A, PIO_PA28E_SDMMC1_CMD, PIO_PERIPH_E, PIO_PULLUP }
- palSetGroupMode(PIOA, PIO_PA28E_SDMMC1_CMD, 0U,
+ palSetGroupMode(PIOA, (1u << PIOA_PIN28), 0U,
PAL_SAMA_FUNC_PERIPH_E | PAL_MODE_INPUT_PULLUP);
/** SDMMC1 pin 4-bit Data (DA0-3) */
- //#define PINS_SDMMC1_DATA4B_IOS1 { PIO_GROUP_A, 0x003c0000, PIO_PERIPH_E, PIO_PULLUP }
palSetGroupMode(PIOA, 0x003c0000, 0U,
PAL_SAMA_FUNC_PERIPH_E | PAL_MODE_INPUT_PULLUP);
@@ -189,8 +157,7 @@ uint8_t sdmmc_device_lowlevelcfg(SdmmcDriver *driver)
driver->config->data_buf_size);
res &= IS_CACHE_ALIGNED(driver->card.EXT);
TRACE_DEBUG_2("check libExt %d %08x\r\n", res, driver->card.EXT);
- //res &= IS_CACHE_ALIGNED(sizeof(driver->card.EXT));
- //TRACE_2("check size libExt %d %08x\r\n",rc,sizeof(driver->card.EXT));
+
if (!res) {
TRACE_WARNING("WARNING: buffers are not aligned on data cache lines. Please fix this before enabling DMA.\n\r");
@@ -218,16 +185,10 @@ bool sdmmc_device_initialize(SdmmcDriver *driver)
driver->blk_size = (val <= 0x2 ? (512 << val) : 512);
- //Configure the TC Timer
-#if SDMMC_USE_TC == 1
- pmc_configure_peripheral(driver->tctimer_id, NULL, true);
- tc_configure(driver->config->tctimer, driver->config->tc_chan, TC_CMR_WAVE | TC_CMR_WAVSEL_UP | TC_CMR_CPCDIS | TC_CMR_BURST_NONE | TC_CMR_TCCLKS_TIMER_CLOCK2);
- driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_EMR |= TC_EMR_NODIVCLK;
-#endif
/* Perform the initial I/O calibration sequence, manually.
* Allow tSTARTUP = 2 usec for the analog circuitry to start up.
* CNTVAL = fHCLOCK / (4 * (1 / tSTARTUP)) */
- val = pmc_get_peripheral_clock(ID_SDMMC0+driver->config->slot_id);
+ val = SAMA_MCK;
val = ROUND_INT_DIV(val, 4 * 500000UL);
@@ -247,7 +208,7 @@ bool sdmmc_device_initialize(SdmmcDriver *driver)
for (exp = 31, power = 1UL << 31; !(val & power) && power != 0;
exp--, power >>= 1) ;
if (power == 0) {
- //trace_warning("FTEOCLK is unknown\n\r");
+ TRACE_DEBUG("FTEOCLK is unknown\n\r");
exp = max_exp;
}
else {
@@ -304,10 +265,6 @@ uint8_t sdmmc_device_start(SdmmcDriver *drv)
return error;
}
- //if (SD_GetStatus(drv) == SDMMC_NOT_SUPPORTED) {
- // TRACE("Device not detected.\n\r");
- // return SDMMC_NOT_SUPPORTED;
- // }
/* Initialization delay: The maximum of 1 msec, 74 clock cycles and supply
* ramp up time. Supply ramp up time provides the time that the power is
@@ -425,23 +382,6 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
Fetch:
/* Fetch normal events */
events = regs->SDMMC_NISTR;
-#if SDMMC_USE_TC == 1
- if (driver->use_polling) {
-
- if (
- driver->expect_auto_end
- && !(driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_SR & TC_SR_CLKSTA)
- )
- events |= SDMMC_NISTR_CUSTOM_EVT;
-
-
- } else {
- if (driver->expect_auto_end) {
- while (driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_SR & TC_SR_CLKSTA);
- events |= SDMMC_NISTR_CUSTOM_EVT;
- }
- }
-#else
if (driver->expect_auto_end)
{
@@ -449,8 +389,6 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
events |= SDMMC_NISTR_CUSTOM_EVT;
}
-
-#endif
if (!events)
return;
//TRACE_1("events %08x\n\r",events);
@@ -669,9 +607,7 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
* Counter for this purpose. */
if (has_data && (cmd->bCmd == 18 || cmd->bCmd == 25)
&& !driver->use_set_blk_cnt) {
-#if SDMMC_USE_TC == 1
- driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
-#endif
+
driver->expect_auto_end = true;
//#ifndef NDEBUG
// if (!set->cmd_line_released)
@@ -742,12 +678,9 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
&& cmd->dwArg & 1ul << 31 && !cmd->cmdOp.bmBits.checkBsy)) {
/* Currently in the function switching period, wait for the
* delay preconfigured in sdmmc_send_command(). */
-#if SDMMC_USE_TC == 1
- driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
- while (driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_SR & TC_SR_CLKSTA) ;
-#else
+
while ( chSysIsCounterWithinX(chSysGetRealtimeCounterX(),driver->start_cycles ,driver->start_cycles+driver->timeout_cycles) );
-#endif
+
}
/* Release this command */
@@ -799,7 +732,7 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
* is 32 whereas the real value is 40.5 */
mult_freq = (regs->SDMMC_CA1R & SDMMC_CA1R_CLKMULT_Msk) >> SDMMC_CA1R_CLKMULT_Pos;
if (mult_freq != 0)
- #if 0
+ #if 1
mult_freq = base_freq * (mult_freq + 1);
#else
mult_freq = pmc_get_gck_clock(ID_SDMMC0+driver->config->slot_id);
@@ -888,9 +821,6 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
uint32_t eister;
uint32_t mask;
uint32_t len;
-#if SDMMC_USE_TC == 1
- uint32_t cycles;
-#endif
uint16_t cr;
uint16_t tmr;
@@ -1113,16 +1043,10 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
* bits, hence 48 device clock cycles.
* The sum of the above timings is the maximum time CMD12 will
* take to complete. */
-#if SDMMC_USE_TC == 1
- cycles = pmc_get_peripheral_clock(driver->tctimer_id) / (driver->dev_freq / (2ul + 64ul + 48ul));
- TRACE_DEBUG_1("[command] has_data wait %d cycles\r\n",cycles);
- /* The Timer operates with RC >= 1 */
- driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_RC = max_u32(cycles, 1);
-#else
driver->timeout_cycles = 2+64+48;
driver->start_cycles = chSysGetRealtimeCounterX();
-#endif
+
}
/* With SD devices, the 8-cycle function switching period will apply,
@@ -1130,14 +1054,10 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
* Note that MMC devices don't require this fixed delay, but regarding
* GO_IDLE_STATE we have no mean to filter the MMC requests out. */
else if (wait_switch) {
-#if SDMMC_USE_TC == 1
- cycles = pmc_get_peripheral_clock(driver->tctimer_id) / (driver->dev_freq / 8ul);
- TRACE_DEBUG_1("[command] wait_switch %d cycles\r\n",cycles);
- driver->config->tctimer->TC_CHANNEL[driver->config->tc_chan].TC_RC = max_u32(cycles, 1);
-#else
+
driver->timeout_ticks = 8;
driver->start_cycles = chSysGetRealtimeCounterX();
-#endif
+
}
if (!driver->use_polling) {
regs->SDMMC_NISIER |= SDMMC_NISIER_BRDRDY | SDMMC_NISIER_BWRRDY | SDMMC_NISIER_TRFC | SDMMC_NISIER_CMDC | SDMMC_NISIER_CINT;
@@ -1160,18 +1080,16 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
*/
uint32_t sdmmc_device_control(SdmmcDriver *driver, uint32_t bCtl)
{
- //osalDbgCheck(driver);
- //struct sdmmc_set *set = (struct sdmmc_set *)_set;
uint32_t rc = SDMMC_OK;
- //uint32_t*param_u32 = (uint32_t *)param;
+
uint8_t byte;
- //#if TRACE_LEVEL >= TRACE_LEVEL_DEBUG
+
if (bCtl != SDMMC_IOCTL_BUSY_CHECK && bCtl != SDMMC_IOCTL_GET_DEVICE) {
TRACE_DEBUG_2("SDMMC_IOCTL_%s(%lu)\n\r", SD_StringifyIOCtrl(bCtl),driver->control_param );
}
- //#endif
+
switch (bCtl) {
case SDMMC_IOCTL_GET_DEVICE:
@@ -1361,12 +1279,12 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
rc = SDMMC_NOT_SUPPORTED;
break;
}
- //#if TRACE_LEVEL >= TRACE_LEVEL_ERROR
+
if (rc != SDMMC_OK && rc != SDMMC_CHANGED
&& bCtl != SDMMC_IOCTL_BUSY_CHECK) {
TRACE_ERROR_2("SDMMC_IOCTL_%s ended with %s\n\r",SD_StringifyIOCtrl(bCtl), SD_StringifyRetCode(rc));
}
- //#endif
+
return rc;
}
@@ -1387,9 +1305,9 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
end = time + (systime_t)t;
do {
- //chSysLock();
+
now = chVTTimeElapsedSinceX(time);
- //chSysUnlock();
+
if (now >= end) {
f = 1;
}
@@ -1409,13 +1327,13 @@ void sdmmc_device_deInit(SdmmcDriver *drv)
void sdmmc_device_checkTimeCount(SdmmcDriver *driver)
{
if (driver->timeout_elapsed != -1) {
- // chSysLock();
+
driver->timeout_elapsed = 0;
driver->now = chVTTimeElapsedSinceX( driver->time);
if (driver->now >= driver->timeout_ticks ) {
driver->timeout_elapsed = 1;
}
- //chSysUnlock();
+
}
}
@@ -2012,4 +1930,6 @@ static uint8_t sdmmc_set_bus_width(SdmmcDriver *driver, uint8_t bits)
return rc;
}
+
+
#endif
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.c b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.c
deleted file mode 100644
index 0d4c2616b..000000000
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.c
+++ /dev/null
@@ -1,835 +0,0 @@
-#include "hal.h"
-
-#if (HAL_USE_SDMMC == TRUE)
-
-#include "sama_sdmmc_lld.h"
-#include "ch_sdmmc_pmc.h"
-
-
-struct _pmc_main_osc {
- uint32_t rc_freq;
- uint32_t crystal_freq;
-};
-
-
-
-enum _slowclock_domain {
- SLOWCLOCK_DOMAIN_DEFAULT, /* Default slow clock, used as input for peripherals */
-#ifdef CONFIG_HAVE_SLOWCLOCK_TIMING_DOMAIN
- SLOWCLOCK_DOMAIN_TIMING, /* Timing Domain slow clock (RTC, RTT) */
-#endif
-};
-
-static uint32_t _pmc_mck = 0;
-static struct _pmc_main_osc _pmc_main_oscillators = {
- .rc_freq = MAIN_CLOCK_INT_OSC,
-};
-
-uint32_t pmc_get_slow_clock(void);
-void pmc_disable_gck(uint32_t id);
-int pmc_select_external_osc(bool bypass);
-void pmc_enable_internal_osc(void);
-void pmc_switch_mck_to_slck(void);
-void pmc_select_internal_osc(void);
-void pmc_disable_external_osc(void);
-void pmc_disable_internal_osc(void);
-
-static uint16_t _pmc_measure_main_osc_freq(bool external_xt)
-{
- volatile uint32_t timeout = MAINFRDY_TIMEOUT;
-
-#ifdef CKGR_MCFR_CCSS
- PMC->CKGR_MCFR = external_xt ? CKGR_MCFR_CCSS : 0;
-#endif
-
-#ifdef CKGR_MCFR_RCMEAS
- PMC->CKGR_MCFR |= CKGR_MCFR_RCMEAS;
-#endif
- timeout = MAINFRDY_TIMEOUT;
- while (!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY) && --timeout > 0);
-
- return (timeout ?
- ((PMC->CKGR_MCFR & CKGR_MCFR_MAINF_Msk) >> CKGR_MCFR_MAINF_Pos) :
- 0u);
-}
-
-void pmc_switch_mck_to_new_source(uint32_t mckr_css)
-{
- uint32_t mckr = PMC->PMC_MCKR;
- uint32_t mask = PMC_MCKR_CSS_Msk;
-
- if ((mckr ^ mckr_css) & mask) {
- PMC->PMC_MCKR = (mckr & ~mask) | (mckr_css & mask);
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
- }
-
- _pmc_mck = 0;
-}
-
-
-uint32_t pmc_set_main_oscillator_freq(uint32_t freq)
-{
- uint32_t mor, mckr, mckr_mask;
- uint16_t mainf_rc, mainf_xt = 0;
-
- _pmc_main_oscillators.crystal_freq = freq;
-
- if (freq > 0)
- return freq;
-#if 1
- /*
- * Save the current value of the CKGR_MCKR register then swith to
- * the slow clock.
- */
- mckr = PMC->PMC_MCKR;
- pmc_switch_mck_to_slck();
- mckr_mask = PMC_MCKR_MDIV_Msk | PMC_MCKR_PRES_Msk;
- PMC->PMC_MCKR &= ~mckr_mask;
-
- /* Save the current value of the CKGR_MOR register. */
- mor = PMC->CKGR_MOR;
-
- /* Measure the 12MHz RC frequency. */
- pmc_select_internal_osc();
- mainf_rc = _pmc_measure_main_osc_freq(false);
-
- /* Measure the crystal or by-pass frequency. */
-
- /* Try by-pass first. */
- if (pmc_select_external_osc(true) == 0)
- mainf_xt = _pmc_measure_main_osc_freq(true);
-
- /* Then try external crytal if no by-pass. */
- if (!mainf_xt) {
- if (pmc_select_external_osc(false) == 0)
- mainf_xt = _pmc_measure_main_osc_freq(true);
- }
-
- /* Switch back to internal 12MHz RC if it was selected initially */
- if (!(mor & CKGR_MOR_MOSCSEL))
- pmc_select_internal_osc();
-
-#ifdef CKGR_MOR_MOSCRCEN
- /* Disable internal oscillator if it wasn't enabled initially */
- if (!(mor & CKGR_MOR_MOSCRCEN))
- pmc_disable_internal_osc();
-#endif
-
- /* Switch back to the former MCK source. */
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~mckr_mask) | (mckr & mckr_mask);
- pmc_switch_mck_to_new_source(mckr & PMC_MCKR_CSS_Msk);
-
- /* Guess the external crystal frequency, if available. */
- if (mainf_rc && mainf_xt) {
- uint32_t ratio = (mainf_xt * 1000) / mainf_rc;
-
- // Use 10% low and high margins
- if (1800 <= ratio && ratio <= 2200) {
- // 24/12 => ratio = 2000
- _pmc_main_oscillators.crystal_freq = 24000000u;
- } else if (1200 <= ratio && ratio <= 1467) {
- // 16/12 => ratio = 1333
- _pmc_main_oscillators.crystal_freq = 16000000u;
- } else if (900 <= ratio && ratio <= 1100) {
- // 12/12 => ratio = 1000
- _pmc_main_oscillators.crystal_freq = 12000000u;
- } else if (600 <= ratio && ratio <= 733) {
- // 8/12 => ratio = 667
- _pmc_main_oscillators.crystal_freq = 8000000u;
- }
- }
-#endif
- return _pmc_main_oscillators.crystal_freq;
-}
-
-bool pmc_is_peripheral_enabled(uint32_t id)
-{
-// assert(id < ID_PERIPH_COUNT);
-
-#ifdef PMC_CSR_PID0
- return (PMC->PMC_CSR[(id >> 5) & 3] & (1 << (id & 31))) != 0;
-#else
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR;
-
- return (pcr & PMC_PCR_EN) != 0;
-#endif
-}
-
-void pmc_enable_peripheral(uint32_t id)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- // select peripheral
- PMC->PMC_PCR = PMC_PCR_PID(id);
-
- volatile uint32_t pcr = PMC->PMC_PCR;
- PMC->PMC_PCR = pcr | PMC_PCR_CMD | PMC_PCR_EN;
-}
-
-void pmc_disable_peripheral(uint32_t id)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- // select peripheral
- PMC->PMC_PCR = PMC_PCR_PID(id);
-
- // disable it but keep previous configuration
- PMC->PMC_PCR = (PMC->PMC_PCR & ~PMC_PCR_EN) | PMC_PCR_CMD;
-}
-
-Matrix* get_peripheral_matrix(uint32_t id)
-{
- //int i;
- switch(id)
- {
- case ID_ARM_PMU: /* 2: Performance Monitor Unit (PMU) (ARM_PMU) */
- case ID_XDMAC0: /* 6: DMA Controller 0 (XDMAC0) */
- case ID_XDMAC1: /* 7: DMA Controller 1 (XDMAC1) */
- case ID_AES: /* 9: Advanced Enion Standard (AES) */
- case ID_AESB: /* 10: AES bridge (AESB) */
- case ID_SHA: /* 12: SHA Signature (SHA) */
- case ID_MPDDRC: /* 13: MPDDR controller (MPDDRC) */
- case ID_MATRIX0: /* 15: H64MX: 64-bit AHB Matrix (MATRIX0) */
- case ID_SDMMC0: /* 31: Secure Digital Multimedia Card Controller 0 (SDMMC0) */
- case ID_SDMMC1: /* 32: Secure Digital Multimedia Card Controller 1 (SDMMC1) */
- case ID_LCDC: /* 45: LCD Controller (LCDC) */
- case ID_ISC: /* 46: Camera Interface (ISC) */
- case ID_QSPI0: /* 52: QSPI 0 (QSPI0) */
- case ID_QSPI1: /* 53: QSPI 1 (QSPI1) */
- case ID_L2CC: /* 63: L2 Cache Controller (L2CC) */
- return MATRIX0; // AHB 64-bit matrix
- default:
- return MATRIX1; // AHB 32-bit matrix
- };
-
-}
-
-uint32_t get_peripheral_clock_matrix_div(uint32_t id)
-{
- Matrix* matrix = get_peripheral_matrix(id);
-
- if (matrix == MATRIX1) {
- if (PMC->PMC_MCKR & PMC_MCKR_H32MXDIV_H32MXDIV2)
- return 2;
- else
- return 1;
- }
-
- return 1;
-}
-
-
-uint32_t pmc_get_peripheral_clock(uint32_t id)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- uint32_t div = get_peripheral_clock_matrix_div(id);
-#ifdef CONFIG_HAVE_PMC_PERIPH_DIV
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR;
- div *= 1 << ((pcr & PMC_PCR_DIV_Msk) >> PMC_PCR_DIV_Pos);
-#endif
-
- return pmc_get_master_clock() / div;
-}
-
-bool slowclock_is_internal(enum _slowclock_domain domain)
-{
- (void)domain;
- return (SCKC->SCKC_CR & SCKC_CR_OSCSEL) != SCKC_CR_OSCSEL;
-}
-
-uint32_t slowclock_get_clock(enum _slowclock_domain domain)
-{
- if (slowclock_is_internal(domain))
- return 32000;
- else
- return 32768;
-}
-
-uint32_t pmc_get_slow_clock(void)
-{
- return slowclock_get_clock(SLOWCLOCK_DOMAIN_DEFAULT);
-}
-
-uint32_t pmc_get_upll_clock(void)
-{
- uint32_t upllclk;
-
-#if defined(SFR_UTMICKTRIM_FREQ_Msk)
- uint32_t clktrim = SFR->SFR_UTMICKTRIM & SFR_UTMICKTRIM_FREQ_Msk;
- switch (clktrim) {
-#ifdef SFR_UTMICKTRIM_FREQ_48
- case SFR_UTMICKTRIM_FREQ_48:
- upllclk = 10 * _pmc_main_oscillators.crystal_freq;
- break;
-#endif
- case SFR_UTMICKTRIM_FREQ_24:
- upllclk = 20 * _pmc_main_oscillators.crystal_freq;
- break;
- case SFR_UTMICKTRIM_FREQ_16:
- upllclk = 30 * _pmc_main_oscillators.crystal_freq;
- break;
- default:
- upllclk = 40 * _pmc_main_oscillators.crystal_freq;
- break;
- }
-#elif defined(UTMI_CKTRIM_FREQ_Msk)
- uint32_t clktrim = UTMI->UTMI_CKTRIM & UTMI_CKTRIM_FREQ_Msk;
- switch (clktrim) {
- case UTMI_CKTRIM_FREQ_XTAL16:
- upllclk = 30 * _pmc_main_oscillators.crystal_freq;
- break;
- default:
- upllclk = 40 * _pmc_main_oscillators.crystal_freq;
- break;
- }
-#else
- upllclk = 40 * _pmc_main_oscillators.crystal_freq;
-#endif
-
-#ifdef CONFIG_HAVE_PMC_UPLLDIV2
- if (PMC->PMC_MCKR & PMC_MCKR_UPLLDIV2)
- upllclk >>= 1;
-#endif
-
- return upllclk;
-}
-
-uint32_t pmc_get_main_clock(void)
-{
- if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
- return _pmc_main_oscillators.crystal_freq; /* external crystal */
- else
- return _pmc_main_oscillators.rc_freq; /* on-chip main clock RC */
-}
-
-uint32_t pmc_get_plla_clock(void)
-{
- uint32_t pllaclk, pllar, pllmula, plldiva;
-
- pllar = PMC->CKGR_PLLAR;
- pllmula = (pllar & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos;
- plldiva = (pllar & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos;
- if (plldiva == 0 || pllmula == 0)
- return 0;
-
- pllaclk = pmc_get_main_clock();
- pllaclk = pllaclk * (pllmula + 1) / plldiva;
-#ifdef CONFIG_HAVE_PMC_PLLADIV2
- if (PMC->PMC_MCKR & PMC_MCKR_PLLADIV2)
- pllaclk >>= 1;
-#endif
- return pllaclk;
-}
-
-uint32_t pmc_get_processor_clock(void)
-{
- uint32_t procclk, mdiv;
-
- procclk = pmc_get_master_clock();
-
- mdiv = PMC->PMC_MCKR & PMC_MCKR_MDIV_Msk;
- switch (mdiv) {
- case PMC_MCKR_MDIV_EQ_PCK:
- break;
- case PMC_MCKR_MDIV_PCK_DIV2:
- procclk <<= 1; // multiply by 2
- break;
- case PMC_MCKR_MDIV_PCK_DIV3:
- procclk *= 3; // multiply by 3
- break;
- case PMC_MCKR_MDIV_PCK_DIV4:
- procclk <<= 2; // multiply by 4
- break;
- default:
- /* should never get here... */
- break;
- }
-
- return procclk;
-}
-
-
-
-static void _pmc_compute_mck(void)
-{
- uint32_t clk = 0;
- uint32_t mckr = PMC->PMC_MCKR;
-
- uint32_t css = mckr & PMC_MCKR_CSS_Msk;
- switch (css) {
- case PMC_MCKR_CSS_SLOW_CLK:
- clk = pmc_get_slow_clock();
- break;
- case PMC_MCKR_CSS_MAIN_CLK:
- clk = pmc_get_main_clock();
- break;
- case PMC_MCKR_CSS_PLLA_CLK:
- clk = pmc_get_plla_clock();
- break;
- case PMC_MCKR_CSS_UPLL_CLK:
- clk = pmc_get_upll_clock();
- break;
- default:
- /* should never get here... */
- break;
- }
-
- uint32_t pres = mckr & PMC_MCKR_PRES_Msk;
- switch (pres) {
- case PMC_MCKR_PRES_CLOCK:
- break;
- case PMC_MCKR_PRES_CLOCK_DIV2:
- clk >>= 1;
- break;
- case PMC_MCKR_PRES_CLOCK_DIV4:
- clk >>= 2;
- break;
- case PMC_MCKR_PRES_CLOCK_DIV8:
- clk >>= 3;
- break;
- case PMC_MCKR_PRES_CLOCK_DIV16:
- clk >>= 4;
- break;
- case PMC_MCKR_PRES_CLOCK_DIV32:
- clk >>= 5;
- break;
- case PMC_MCKR_PRES_CLOCK_DIV64:
- clk >>= 6;
- break;
-#ifdef PMC_MCKR_PRES_CLOCK_DIV3
- case PMC_MCKR_PRES_CLOCK_DIV3:
- clk /= 3;
- break;
-#endif
- default:
- /* should never get here... */
- break;
- }
-
- uint32_t mdiv = mckr & PMC_MCKR_MDIV_Msk;
- switch (mdiv) {
- case PMC_MCKR_MDIV_EQ_PCK:
- break;
- case PMC_MCKR_MDIV_PCK_DIV2:
- clk >>= 1; // divide by 2
- break;
- case PMC_MCKR_MDIV_PCK_DIV4:
- clk >>= 2; // divide by 4
- break;
- case PMC_MCKR_MDIV_PCK_DIV3:
- clk /= 3; // divide by 3
- break;
- default:
- /* should never get here... */
- break;
- }
-
- _pmc_mck = clk;
-}
-
-uint32_t pmc_get_master_clock(void)
-{
- if (!_pmc_mck)
- _pmc_compute_mck();
- return _pmc_mck;
-}
-
-
-void pmc_configure_gck(uint32_t id, uint32_t clock_source, uint32_t div)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
- osalDbgCheck(!(clock_source & ~PMC_PCR_GCKCSS_Msk));
- osalDbgCheck(div > 0);
- osalDbgCheck(!((div << PMC_PCR_GCKDIV_Pos) & ~PMC_PCR_GCKDIV_Msk));
-
- pmc_disable_gck(id);
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR & ~(PMC_PCR_GCKCSS_Msk | PMC_PCR_GCKDIV_Msk);
- PMC->PMC_PCR = pcr | clock_source | PMC_PCR_CMD | PMC_PCR_GCKDIV(div - 1);
-}
-
-
-void pmc_enable_gck(uint32_t id)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR;
- PMC->PMC_PCR = pcr | PMC_PCR_CMD | PMC_PCR_GCKEN;
-
-#ifdef PMC_GCSR_PID0
- while ((PMC->PMC_GCSR[(id >> 5) & 3] & (1 << (id & 31))) == 0);
-#else
- while (!(PMC->PMC_SR & PMC_SR_GCKRDY));
-#endif
-}
-
-void pmc_disable_gck(uint32_t id)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR;
- PMC->PMC_PCR = PMC_PCR_CMD | (pcr & ~PMC_PCR_GCKEN);
-}
-
-uint32_t pmc_get_gck_clock(uint32_t id)
-{
- uint32_t clk = 0;
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- PMC->PMC_PCR = PMC_PCR_PID(id);
- volatile uint32_t pcr = PMC->PMC_PCR;
-
- switch (pcr & PMC_PCR_GCKCSS_Msk) {
- case PMC_PCR_GCKCSS_SLOW_CLK:
- clk = pmc_get_slow_clock();
- break;
- case PMC_PCR_GCKCSS_MAIN_CLK:
- clk = pmc_get_main_clock();
- break;
- case PMC_PCR_GCKCSS_PLLA_CLK:
- clk = pmc_get_plla_clock();
- break;
- case PMC_PCR_GCKCSS_UPLL_CLK:
- clk = pmc_get_upll_clock();
- break;
- case PMC_PCR_GCKCSS_MCK_CLK:
- clk = pmc_get_master_clock();
- break;
-#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK
- case PMC_PCR_GCKCSS_AUDIO_CLK:
- clk = pmc_get_audio_pmc_clock();
- break;
-#endif
- }
-
- uint32_t div = (pcr & PMC_PCR_GCKDIV_Msk) >> PMC_PCR_GCKDIV_Pos;
- return ROUND_INT_DIV(clk, div + 1);
-}
-
-void pmc_configure_peripheral(uint32_t id, const struct _pmc_periph_cfg* cfg, bool enable)
-{
- osalDbgCheck(id < ID_PERIPH_COUNT);
-
- pmc_disable_peripheral(id);
-
- if (cfg != NULL) {
-
- if (cfg->gck.div > 0)
- pmc_configure_gck(id, cfg->gck.css, cfg->gck.div);
-
- } else {
- pmc_disable_gck(id);
- }
-
- /* Enable peripheral, gck or only configure it */
- if (enable) {
- if (cfg && cfg->gck.div > 0)
- pmc_enable_gck(id);
-
- pmc_enable_peripheral(id);
- }
-}
-
-
-void pmc_enable_upll_clock(void)
-{
- uint32_t uckr = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3);
- uckr |= CKGR_UCKR_BIASCOUNT(0x1);
-
-
-#if defined(SFR_UTMICKTRIM_FREQ_Msk)
- switch (_pmc_main_oscillators.crystal_freq) {
-#ifdef SFR_UTMICKTRIM_FREQ_48
- case 48000000:
- SFR->SFR_UTMICKTRIM = (SFR->SFR_UTMICKTRIM & ~SFR_UTMICKTRIM_FREQ_Msk) | SFR_UTMICKTRIM_FREQ_48;
- break;
-#endif
- case 24000000:
- SFR->SFR_UTMICKTRIM = (SFR->SFR_UTMICKTRIM & ~SFR_UTMICKTRIM_FREQ_Msk) | SFR_UTMICKTRIM_FREQ_24;
- break;
- case 16000000:
- SFR->SFR_UTMICKTRIM = (SFR->SFR_UTMICKTRIM & ~SFR_UTMICKTRIM_FREQ_Msk) | SFR_UTMICKTRIM_FREQ_16;
- break;
- default:
- SFR->SFR_UTMICKTRIM = (SFR->SFR_UTMICKTRIM & ~SFR_UTMICKTRIM_FREQ_Msk) | SFR_UTMICKTRIM_FREQ_12;
- }
-#elif defined(UTMI_CKTRIM_FREQ_Msk)
- switch (_pmc_main_oscillators.crystal_freq) {
- case 16000000:
- UTMI->UTMI_CKTRIM = (UTMI->UTMI_CKTRIM & ~UTMI_CKTRIM_FREQ_Msk) | UTMI_CKTRIM_FREQ_XTAL16;
- break;
- default:
- UTMI->UTMI_CKTRIM = (UTMI->UTMI_CKTRIM & ~UTMI_CKTRIM_FREQ_Msk) | UTMI_CKTRIM_FREQ_XTAL12;
- }
-#endif
-
- /* enable the 480MHz UTMI PLL */
- PMC->CKGR_UCKR = uckr;
-
- /* wait until UPLL is locked */
- while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-}
-
-
-void pmc_enable_upll_bias(void)
-{
- PMC->CKGR_UCKR |= CKGR_UCKR_BIASEN;
-}
-
-void pmc_disable_upll_bias(void)
-{
- PMC->CKGR_UCKR &= ~CKGR_UCKR_BIASEN;
-}
-
-void pmc_switch_mck_to_slck(void)
-{
- /* Select Slow Clock as input clock for PCK and MCK */
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_SLOW_CLK;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- _pmc_mck = 0;
-}
-
-void pmc_select_internal_osc(void)
-{
- pmc_enable_internal_osc();
-
- /* switch MAIN clock to internal 12MHz RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCSEL | CKGR_MOR_KEY_Msk)) | CKGR_MOR_KEY_PASSWD;
-
- /* in case where MCK is running on MAIN CLK */
- if ((PMC->PMC_MCKR & PMC_MCKR_CSS_PLLA_CLK) || (PMC->PMC_MCKR & PMC_MCKR_CSS_MAIN_CLK))
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* disable external OSC 12 MHz to save power*/
- pmc_disable_external_osc();
-}
-
-int pmc_enable_external_osc(bool bypass)
-{
- uint32_t cgmor = PMC->CKGR_MOR;
- uint32_t mask = CKGR_MOR_MOSCXTEN;
- volatile uint32_t timeout;
-
- if (bypass)
- mask = CKGR_MOR_MOSCXTBY;
-
- /* Enable Crystal Oscillator if needed */
- if ((cgmor & mask) != mask) {
- cgmor &= ~CKGR_MOR_KEY_Msk;
- cgmor |= CKGR_MOR_KEY_PASSWD;
-
- if (bypass) {
- /* Disable Crystal Oscillator */
- cgmor &= ~CKGR_MOR_MOSCXTEN;
- PMC->CKGR_MOR = cgmor;
-
- /* Wait Main Oscillator not ready */
- while (PMC->PMC_SR & PMC_SR_MOSCXTS);
-
- /* Enable Crystal Oscillator Bypass */
- cgmor |= CKGR_MOR_MOSCXTBY;
- PMC->CKGR_MOR = cgmor;
- } else {
- /* Disable Crystal Oscillator Bypass */
- cgmor &= ~CKGR_MOR_MOSCXTBY;
- PMC->CKGR_MOR = cgmor;
-
- /* Wait Main Oscillator not ready */
- while (PMC->PMC_SR & PMC_SR_MOSCXTS);
-
- /* Set Oscillator Startup Time */
- cgmor &= ~CKGR_MOR_MOSCXTST_Msk;
- cgmor |= CKGR_MOR_MOSCXTST(18);
- PMC->CKGR_MOR = cgmor;
-
- /* Enable Crystal Oscillator */
- cgmor |= CKGR_MOR_MOSCXTEN;
- PMC->CKGR_MOR = cgmor;
- }
-
- /* Wait Main Oscillator ready */
- timeout = MOSCXTS_TIMEOUT;
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && --timeout > 0);
-
- /* Return true if oscillator ready before timeout */
- return timeout == 0 ? -1 : 0;
- } else {
- /* Crystal Oscillator already selected, just check if ready */
- if (PMC->PMC_SR & PMC_SR_MOSCXTS)
- return 0;
- else
- return -2;
- }
-}
-
-void pmc_disable_external_osc(void)
-{
- /* disable external OSC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCSEL | CKGR_MOR_KEY_Msk)) | CKGR_MOR_KEY_PASSWD;
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTBY | CKGR_MOR_KEY_Msk)) | CKGR_MOR_KEY_PASSWD;
-}
-int pmc_select_external_osc(bool bypass)
-{
- int err;
- volatile uint32_t timeout;
-
- /* Return if external oscillator had been selected */
- if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) == CKGR_MOR_MOSCSEL) {
- uint32_t mask = bypass ? CKGR_MOR_MOSCXTBY : CKGR_MOR_MOSCXTEN;
- if ((PMC->CKGR_MOR & mask) == mask)
- return 0;
- }
-
- /*
- * When switching the source of the main clock between the RC oscillator and the crystal
- * oscillator, both oscillators must be enabled. After completion of the switch, the
- * unused oscillator can be disabled.
- */
- pmc_enable_internal_osc();
- err = pmc_enable_external_osc(bypass);
- if (err < 0)
- return err;
-
- /* switch MAIN clock to external oscillator */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_KEY_Msk) | CKGR_MOR_MOSCSEL
- | CKGR_MOR_KEY_PASSWD;
-
- /* wait for the command to be taken into account */
- while ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) != CKGR_MOR_MOSCSEL);
-
- /* wait MAIN clock status change for external oscillator selection */
- timeout = MOSCSELS_TIMEOUT;
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && --timeout > 0);
- if (!timeout) {
- PMC->CKGR_MOR &= ~CKGR_MOR_MOSCSEL;
- return -1;
- }
-
- /* in case where MCK is running on MAIN CLK */
- if ((PMC->PMC_MCKR & PMC_MCKR_CSS_PLLA_CLK) || (PMC->PMC_MCKR & PMC_MCKR_CSS_MAIN_CLK))
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* disable internal 12MHz RC to save power */
- pmc_disable_internal_osc();
-
- return 0;
-}
-
-
-void pmc_enable_internal_osc(void)
-{
-#ifdef CKGR_MOR_MOSCRCEN
- /* Enable internal 12MHz RC when needed */
- if ((PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN) != CKGR_MOR_MOSCRCEN) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_KEY_Msk) | CKGR_MOR_MOSCRCEN | CKGR_MOR_KEY_PASSWD;
- /* Wait internal 12MHz RC Startup Time for clock stabilization */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
- }
-#endif
-}
-
-void pmc_switch_mck_to_pll(void)
-{
- /* Select PLL as input clock for PCK and MCK */
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- _pmc_mck = 0;
-}
-
-void pmc_set_mck_prescaler(uint32_t prescaler)
-{
- //assert(!(prescaler & ~PMC_MCKR_PRES_Msk));
-
- /* Change MCK Prescaler divider in PMC_MCKR register */
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | prescaler;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-
-#ifdef CONFIG_HAVE_PMC_H32MXDIV
-void pmc_set_mck_h32mxdiv(bool div2)
-{
- uint32_t mckr = PMC->PMC_MCKR;
- if (div2) {
- if ((mckr & PMC_MCKR_H32MXDIV) != PMC_MCKR_H32MXDIV_H32MXDIV2)
- PMC->PMC_MCKR = (mckr & ~PMC_MCKR_H32MXDIV) | PMC_MCKR_H32MXDIV_H32MXDIV2;
- } else {
- if ((mckr & PMC_MCKR_H32MXDIV) != PMC_MCKR_H32MXDIV_H32MXDIV1)
- PMC->PMC_MCKR = (mckr & ~PMC_MCKR_H32MXDIV) | PMC_MCKR_H32MXDIV_H32MXDIV1;
- }
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-#endif /* CONFIG_HAVE_PMC_H32MXDIV */
-
-#ifdef CONFIG_HAVE_PMC_PLLADIV2
-void pmc_set_mck_plladiv2(bool div2)
-{
- uint32_t mckr = PMC->PMC_MCKR;
- if (div2) {
- if ((mckr & PMC_MCKR_PLLADIV2) != PMC_MCKR_PLLADIV2)
- PMC->PMC_MCKR = mckr | PMC_MCKR_PLLADIV2;
- } else {
- if ((mckr & PMC_MCKR_PLLADIV2) == PMC_MCKR_PLLADIV2)
- PMC->PMC_MCKR = mckr & ~PMC_MCKR_PLLADIV2;
- }
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-#endif
-
-void pmc_set_mck_divider(uint32_t divider)
-{
- //assert(!(divider & ~PMC_MCKR_MDIV_Msk));
-
- /* change MCK Prescaler divider in PMC_MCKR register */
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk) | divider;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-void pmc_configure_plla(const struct _pmc_plla_cfg* plla)
-{
- uint32_t pllar = 0;
-
-#ifdef CKGR_PLLAR_ONE
- pllar |= CKGR_PLLAR_ONE;
-#endif
- pllar |= CKGR_PLLAR_MULA(plla->mul);
- pllar |= CKGR_PLLAR_DIVA(plla->div);
- pllar |= CKGR_PLLAR_PLLACOUNT(plla->count);
- PMC->CKGR_PLLAR = pllar;
-
-#ifdef CONFIG_HAVE_PMC_PLLA_CHARGEPUMP
- PMC->PMC_PLLICPR = plla->icp & PMC_PLLICPR_ICP_PLLA_Msk;
-#endif /* CONFIG_HAVE_PMC_PLLA_CHARGEPUMP */
-
- if (plla->mul > 0)
- while (!(PMC->PMC_SR & PMC_SR_LOCKA));
-}
-
-void pmc_disable_plla(void)
-{
- PMC->CKGR_PLLAR = (PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk) | CKGR_PLLAR_MULA(0);
-}
-
-
-
-
-
-
-void pmc_disable_internal_osc(void)
-{
-#ifdef CKGR_MOR_MOSCRCEN
- /* disable internal 12MHz RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_KEY_Msk) | CKGR_MOR_KEY_PASSWD;
-#endif
-}
-
-
-#endif
-
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.h b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.h
deleted file mode 100644
index 2400ce842..000000000
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef CH_SDMMC_PMC_H_
-#define CH_SDMMC_PMC_H_
-
-
-struct _pmc_plla_cfg {
- /** PLLA MUL value */
- uint32_t mul;
-
- /** PLLA DIV value */
- uint32_t div;
-
- /** PLLA COUNT value (number of slow clock cycles before the PLLA is locked) */
- uint32_t count;
-
-#ifdef CONFIG_HAVE_PMC_PLLA_CHARGE_PUMP
- /** PLLA ICP value */
- uint32_t icp;
-#endif
-};
-
-struct _pmc_periph_cfg{
-
- struct {
- /** gck source selection: SLOW, MAIN, PLLA, UPLL, MCK or AUDIO */
- uint32_t css;
- /** gck division ratio (0 means disable, n >= 1 divide by n) */
- uint32_t div;
- } gck;
-
-};
-
-#define pmcEnableSDMMC0() pmcEnablePidLow(ID_SDMMC0_MSK)
-#define pmcDisableSDMMC0() pmcDisablePidLow(ID_SDMMC0_MSK)
-
-#define pmcEnableSDMMC1() pmcEnablePidHigh(ID_SDMMC1_MSK)
-#define pmcDisableSDMMC1() pmcDisablePidHigh(ID_SDMMC1_MSK)
-
-
-extern void pmc_configure_peripheral(uint32_t id, const struct _pmc_periph_cfg* cfg, bool enable);
-extern void pmc_enable_upll_clock(void);
-extern void pmc_enable_upll_bias(void);
-extern uint32_t pmc_get_peripheral_clock(uint32_t id);
-extern uint32_t pmc_get_master_clock(void);
-extern uint32_t pmc_get_gck_clock(uint32_t id);
-extern bool pmc_is_peripheral_enabled(uint32_t id);
-extern uint32_t pmc_set_main_oscillator_freq(uint32_t freq);
-extern uint32_t pmc_get_slow_clock(void);
-extern uint32_t pmc_get_processor_clock(void);
-
-#endif /* CH_SDMMC_PMC_H_ */
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sama5d2.h b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sama5d2.h
index ae05cee2f..adbd63a41 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sama5d2.h
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sama5d2.h
@@ -10,56 +10,12 @@
#define SDMMC_BUFFER_SIZE (EXT_SIZE + SSR_SIZE + SCR_SIZE + SB1_SIZE + SB2_SIZE)
-/** Frequency of the board main clock oscillator */
-#define BOARD_MAIN_CLOCK_EXT_OSC 12000000
-#define MAIN_CLOCK_INT_OSC 12000000
-#define OSC_STARTUP_TIME 0xFFu
-#define MAINFRDY_TIMEOUT 32u
-#define MOSCXTS_TIMEOUT ((OSC_STARTUP_TIME * 8) + 8)
-#define MOSCSELS_TIMEOUT 32u
-
-
typedef enum
{
SDMMC_SLOT0 = 0,
SDMMC_SLOT1
}sdmmcslots_t;
-#define CONFIG_HAVE_PMIC_ACT8945A 0
-#define CONFIG_HAVE_PMC_PLLADIV2 1
-#define CONFIG_HAVE_PMC_H32MXDIV 1
-
-/* ========== Pio definition for SDMMC0 peripheral ========== */
-#define PIO_PA13A_SDMMC0_CD (1u << 13) /**< \brief Sdmmc0 signal: SDMMC0_CD */
-#define PIO_PA11A_SDMMC0_VDDSEL (1u << 11)/**< \brief Sdmmc0 signal: SDMMC0_VDDSEL */
-#define PIO_PA10A_SDMMC0_RSTN (1u << 10) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */
-#define PIO_PA0A_SDMMC0_CK (1u << 0) /**< \brief Sdmmc0 signal: SDMMC0_CK */
-#define PIO_PA1A_SDMMC0_CMD (1u << 1) /**< \brief Sdmmc0 signal: SDMMC0_CMD */
-#define PIO_PA12A_SDMMC0_WP (1u << 12) /**< \brief Sdmmc0 signal: SDMMC0_WP */
-#define PIO_PA2A_SDMMC0_DAT0 (1u << 2) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */
-#define PIO_PA3A_SDMMC0_DAT1 (1u << 3) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */
-#define PIO_PA4A_SDMMC0_DAT2 (1u << 4) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */
-#define PIO_PA5A_SDMMC0_DAT3 (1u << 5) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */
-#define PIO_PA6A_SDMMC0_DAT4 (1u << 6) /**< \brief Sdmmc0 signal: SDMMC0_DAT4 */
-#define PIO_PA7A_SDMMC0_DAT5 (1u << 7) /**< \brief Sdmmc0 signal: SDMMC0_DAT5 */
-#define PIO_PA8A_SDMMC0_DAT6 (1u << 8) /**< \brief Sdmmc0 signal: SDMMC0_DAT6 */
-#define PIO_PA9A_SDMMC0_DAT7 (1u << 9) /**< \brief Sdmmc0 signal: SDMMC0_DAT7 */
-
-/* ========== Pio PIN definition for SDMMC0 peripheral ========== */
-
-
-/* ========== Pio definition for SDMMC1 peripheral ========== */
-#define PIO_PA30E_SDMMC1_CD (1u << 30) /**< \brief Sdmmc1 signal: SDMMC1_CD */
-#define PIO_PA27E_SDMMC1_RSTN (1u << 27) /**< \brief Sdmmc1 signal: SDMMC1_RSTN */
-#define PIO_PA22E_SDMMC1_CK (1u << 22) /**< \brief Sdmmc1 signal: SDMMC1_CK */
-#define PIO_PA28E_SDMMC1_CMD (1u << 28) /**< \brief Sdmmc1 signal: SDMMC1_CMD */
-#define PIO_PA29E_SDMMC1_WP (1u << 29) /**< \brief Sdmmc1 signal: SDMMC1_WP */
-#define PIO_PA18E_SDMMC1_DAT0 (1u << 18) /**< \brief Sdmmc1 signal: SDMMC1_DAT0 */
-#define PIO_PA19E_SDMMC1_DAT1 (1u << 19) /**< \brief Sdmmc1 signal: SDMMC1_DAT1 */
-#define PIO_PA20E_SDMMC1_DAT2 (1u << 20) /**< \brief Sdmmc1 signal: SDMMC1_DAT2 */
-#define PIO_PA21E_SDMMC1_DAT3 (1u << 21) /**< \brief Sdmmc1 signal: SDMMC1_DAT3 */
-
-
/* mask for board capabilities defines: voltage, slot type and 8-bit support */
#define CAPS0_MASK (SDMMC_CA0R_V33VSUP | SDMMC_CA0R_V30VSUP | \
SDMMC_CA0R_V18VSUP | SDMMC_CA0R_SLTYPE_Msk | \
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.c b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.c
deleted file mode 100644
index 00f8a998e..000000000
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.c
+++ /dev/null
@@ -1,258 +0,0 @@
-#include "hal.h"
-
-#if (HAL_USE_SDMMC == TRUE)
-
-#include "sama_sdmmc_lld.h"
-#include "ch_sdmmc_pmc.h"
-#include "ch_sdmmc_tc.h"
-
-#if SDMMC_USE_TC == 1
-
-/*------------------------------------------------------------------------------
- * Global functions
- *------------------------------------------------------------------------------*/
-uint32_t get_tc_id_from_addr(const Tc* addr, uint8_t channel)
-{
- (void)channel;
-#ifdef TC0
- if (addr == TC0)
-#ifdef ID_TC0_CH0
- return ID_TC0 + channel;
-#else
- return ID_TC0;
-#endif
-#endif
-
-#ifdef TC1
- if (addr == TC1)
-#ifdef ID_TC1_CH0
- return ID_TC1 + channel;
-#else
- return ID_TC1;
-#endif
-#endif
-
-#ifdef TC2
- if (addr == TC2)
-#ifdef ID_TC2_CH0
- return ID_TC2 + channel;
-#else
- return ID_TC2;
-#endif
-#endif
-
-#ifdef TC3
- if (addr == TC3)
-#ifdef ID_TC3_CH0
- return ID_TC3 + channel;
-#else
- return ID_TC3;
-#endif
-#endif
- return ID_PERIPH_COUNT;
-}
-void tc_configure(Tc *tc, uint32_t channel, uint32_t mode)
-{
- TcChannel *ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- /* Disable TC clock */
- ch->TC_CCR = TC_CCR_CLKDIS;
-
- /* Disable interrupts */
- ch->TC_IDR = ch->TC_IMR;
-
- /* Clear status register */
- ch->TC_SR;
-
- /* Set mode */
- ch->TC_CMR = mode;
-}
-
-void tc_start(Tc *tc, uint32_t channel)
-{
- TcChannel *ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- /* Clear status register */
- ch->TC_SR;
-
- ch->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
-}
-
-void tc_stop(Tc *tc, uint32_t channel)
-{
- TcChannel *ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- ch->TC_CCR = TC_CCR_CLKDIS;
-}
-
-void tc_enable_it(Tc *tc, uint32_t channel, uint32_t mask)
-{
- TcChannel *ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- ch->TC_IER = mask;
-}
-
-void tc_disable_it(Tc *tc, uint32_t channel, uint32_t mask)
-{
- TcChannel *ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- ch->TC_IDR = mask;
-}
-
-uint32_t tc_find_best_clock_source(Tc *tc, uint8_t channel, uint32_t freq)
-{
- const int tcclks[] = {
- TC_CMR_TCCLKS_TIMER_CLOCK1,
- TC_CMR_TCCLKS_TIMER_CLOCK2,
- TC_CMR_TCCLKS_TIMER_CLOCK3,
- TC_CMR_TCCLKS_TIMER_CLOCK4,
- TC_CMR_TCCLKS_TIMER_CLOCK5,
- };
- int i, best, higher;
- int best_freq, higher_freq;
-
- best = higher = -1;
- best_freq = higher_freq = 0;
- for (i = 0 ; i <(int) ARRAY_SIZE(tcclks) ; i++) {
- uint32_t f = tc_get_available_freq(tc, channel, tcclks[i]);
- if ( higher < 0 || (f > ((uint32_t)higher_freq) ) ) {
- higher_freq = f;
- higher = tcclks[i];
- }
- if (f > freq) {
- if (best < 0 || (f - freq) < (f - best_freq)) {
- best_freq = f;
- best = tcclks[i];
- }
- }
- }
-
- if (best < 0)
- best = higher;
-
- return best;
-}
-
-uint32_t tc_get_status(Tc *tc, uint32_t channel)
-{
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- return tc->TC_CHANNEL[channel].TC_SR;
-}
-
-uint32_t tc_get_available_freq(Tc *tc, uint8_t channel, uint8_t tc_clks)
-{
- uint32_t tc_id = get_tc_id_from_addr(tc, channel);
-
- switch (tc_clks) {
- case TC_CMR_TCCLKS_TIMER_CLOCK1:
-#ifdef CONFIG_HAVE_PMC_GENERATED_CLOCKS
- if (pmc_is_gck_enabled(tc_id))
- return pmc_get_gck_clock(tc_id);
- else
- return 0;
-#else
- return pmc_get_peripheral_clock(tc_id) >> 1;
-#endif
- case TC_CMR_TCCLKS_TIMER_CLOCK2:
- return pmc_get_peripheral_clock(tc_id) >> 3;
- case TC_CMR_TCCLKS_TIMER_CLOCK3:
- return pmc_get_peripheral_clock(tc_id) >> 5;
- case TC_CMR_TCCLKS_TIMER_CLOCK4:
- return pmc_get_peripheral_clock(tc_id) >> 7;
- case TC_CMR_TCCLKS_TIMER_CLOCK5:
- return pmc_get_slow_clock();
- default:
- return 0;
- }
-}
-
-uint32_t tc_get_channel_freq(Tc *tc, uint32_t channel)
-{
- TcChannel* ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- return tc_get_available_freq(tc, channel, ch->TC_CMR & TC_CMR_TCCLKS_Msk);
-}
-
-void tc_set_ra_rb_rc(Tc *tc, uint32_t channel,
- uint32_t *ra, uint32_t *rb, uint32_t *rc)
-{
- TcChannel* ch;
-
- //assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
-// assert(!(ra && rb) || (ch->TC_CMR & TC_CMR_WAVE));
-
- if (ra)
- ch->TC_RA = *ra;
- if (rb)
- ch->TC_RB = *rb;
- if (rc)
- ch->TC_RC = *rc;
-}
-
-void tc_get_ra_rb_rc(Tc *tc, uint32_t channel,
- uint32_t *ra, uint32_t *rb, uint32_t *rc)
-{
- TcChannel* ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- if (ra)
- *ra = ch->TC_RA;
- if (rb)
- *rb = ch->TC_RB;
- if (rc)
- *rc = ch->TC_RC;
-}
-
-#ifdef CONFIG_HAVE_TC_FAULT_MODE
-
-void tc_set_fault_mode(Tc *tc, uint32_t mode)
-{
- tc->TC_FMR = mode;
-}
-
-#endif /* CONFIG_HAVE_TC_FAULT_MODE */
-
-uint32_t tc_get_cv(Tc* tc, uint32_t channel)
-{
- TcChannel* ch;
-
-// assert(channel < ARRAY_SIZE(tc->TC_CHANNEL));
-
- ch = &tc->TC_CHANNEL[channel];
-
- return ch->TC_CV;
-}
-
-#endif
-#endif
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.h b/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.h
deleted file mode 100644
index 1cce7cb85..000000000
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-#ifndef OS_HAL_PORTS_SAMA_LLD_SDMMCV0__SAMA_SDMMC_TC_H_
-#define OS_HAL_PORTS_SAMA_LLD_SDMMCV0__SAMA_SDMMC_TC_H_
-
-
-extern void tc_configure(Tc *tc, uint32_t channel, uint32_t mode);
-extern void tc_start(Tc *tc, uint32_t channel);
-extern void tc_stop(Tc *tc, uint32_t channel);
-extern void tc_enable_it(Tc *tc, uint32_t channel, uint32_t mask);
-extern void tc_disable_it(Tc *tc, uint32_t channel, uint32_t mask);
-extern uint32_t tc_find_best_clock_source(Tc *tc, uint8_t channel, uint32_t freq);
-extern uint32_t tc_get_status(Tc *tc, uint32_t channel);
-extern uint32_t tc_get_available_freq(Tc *tc, uint8_t channel, uint8_t tc_clks);
-extern uint32_t tc_get_channel_freq(Tc *tc, uint32_t channel);
-extern void tc_set_ra_rb_rc(Tc *tc, uint32_t channel,uint32_t *ra, uint32_t *rb, uint32_t *rc);
-extern void tc_get_ra_rb_rc(Tc *tc, uint32_t channel,uint32_t *ra, uint32_t *rb, uint32_t *rc);
-extern uint32_t tc_get_cv(Tc* tc, uint32_t channel);
-
-extern uint32_t get_tc_id_from_addr(const Tc* addr, uint8_t channel);
-
-#endif /* OS_HAL_PORTS_SAMA_LLD_SDMMCV0__SAMA_SDMMC_TC_H_ */
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/driver.mk b/os/hal/ports/SAMA/LLD/SDMMCv1/driver.mk
index 13494bdc2..5b31411d5 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/driver.mk
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/driver.mk
@@ -2,12 +2,10 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_device.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sdio.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_cmds.c \
- $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_tc.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_mmc.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_sd.c \
$(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc.c \
- $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_ff.c \
- $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_pmc.c
+ $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1/ch_sdmmc_ff.c
PLATFORMINC += $(CHIBIOS)/os/hal/ports/SAMA/LLD/SDMMCv1
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_conf.h b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_conf.h
index 0fb377549..72314ba1a 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_conf.h
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_conf.h
@@ -23,9 +23,6 @@ typedef FATFS CH_SDMMC_FAT;
#define SDMMC_BLOCK_SIZE 512
#endif
-#ifndef SDMMC_USE_TC
-#define SDMMC_USE_TC 0
-#endif
#endif //SAMA_SDMMC_CONF_H
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c
index f21aca143..2c5a862e1 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.c
@@ -24,6 +24,7 @@
#include "hal.h"
#include "ccportab.h"
+
#if (HAL_USE_SDMMC == TRUE) || defined(__DOXYGEN__)
#include <string.h>
#include "sama_sdmmc_lld.h"
@@ -31,10 +32,13 @@
#include "ch_sdmmc_sd.h"
#include "ch_sdmmc_sdio.h"
#include "ch_sdmmc_trace.h"
+
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
-
+#if SAMA_ST_USE_PIT == FALSE
+#error "SDMMC Driver needs SAMA_ST_USE_PIT"
+#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
diff --git a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.h b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.h
index 7093dd9b3..488b57491 100644
--- a/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.h
+++ b/os/hal/ports/SAMA/LLD/SDMMCv1/sama_sdmmc_lld.h
@@ -75,14 +75,6 @@ typedef struct {
sdmmcslots_t slot_id;
- struct _pmc_periph_cfg pmccfg;
-
- bool use_fastest_clock;
-#if SDMMC_USE_TC == 1
- Tc * tctimer;
- uint8_t tc_chan;
-#endif
-
uint8_t * bp;
uint8_t * data_buf;
uint32_t data_buf_size;
@@ -129,10 +121,10 @@ struct SamaSDMMCDriver
uint32_t timeout_ticks;
int8_t timeout_elapsed;
systime_t time,now;
-#if SDMMC_USE_TC == 0
+
rtcnt_t timeout_cycles;
rtcnt_t start_cycles;
-#endif
+
};
typedef sSdCard sdmmclib;
diff --git a/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h b/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h
index 7375b4f6b..611cc9d05 100644
--- a/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h
+++ b/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h
@@ -490,6 +490,33 @@
*/
#define pmcDisableSEC() pmcDisablePidLow(ID_SECUMOD_MSK)
+/**
+ * @brief Enables the SDMMC0 peripheral clock.
+ *
+ * @api
+ */
+#define pmcEnableSDMMC0() pmcEnablePidLow(ID_SDMMC0_MSK)
+
+/**
+ * @brief Disables the SDMMC0 peripheral clock.
+ *
+ * @api
+ */
+#define pmcDisableSDMMC0() pmcDisablePidLow(ID_SDMMC0_MSK)
+
+/**
+ * @brief Enables the SDMMC1 peripheral clock.
+ *
+ * @api
+ */
+#define pmcEnableSDMMC1() pmcEnablePidHigh(ID_SDMMC1_MSK)
+
+/**
+ * @brief Disables the SDMMC1 peripheral clock.
+ *
+ * @api
+ */
+#define pmcDisableSDMMC1() pmcDisablePidHigh(ID_SDMMC1_MSK)
/** @} */
diff --git a/testhal/ATSAMA5D2/SDMMC/main.c b/testhal/ATSAMA5D2/SDMMC/main.c
index ee87869b8..978453d25 100644
--- a/testhal/ATSAMA5D2/SDMMC/main.c
+++ b/testhal/ATSAMA5D2/SDMMC/main.c
@@ -53,25 +53,10 @@ static THD_FUNCTION(Thread1, arg) {
}
}
-//for emmc
-#define CFG_FASTEST { \
- PMC_PCR_GCKCSS_UPLL_CLK, \
- 1, \
- }
-#define CFG_SDMMC { \
- PMC_PCR_GCKCSS_PLLA_CLK, \
- 1, \
- }
static const SamaSDMMCConfig sdmmc_slot1_cfg = {
SDMMC_SLOT1,
- { CFG_SDMMC },
- false,
-#if SDMMC_USE_TC == 1
- TC0,
- 0,
-#endif
sdmmcbuffer,
data_buf,
sizeof(data_buf),
diff --git a/testhal/ATSAMA5D2/SDMMC/mcuconf.h b/testhal/ATSAMA5D2/SDMMC/mcuconf.h
index 0c7f64108..1d2651a62 100644
--- a/testhal/ATSAMA5D2/SDMMC/mcuconf.h
+++ b/testhal/ATSAMA5D2/SDMMC/mcuconf.h
@@ -82,7 +82,9 @@
/*
* SECUMOD
*/
-#define HAL_USE_SECUMOD TRUE
+#define SAMA_ST_USE_PIT TRUE
+#define SAMA_ST_USE_TC0 FALSE
+#define SAMA_ST_USE_TC1 FALSE
/*
* TC driver system settings.
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 13:27:16 +0000