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Diffstat (limited to 'os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld')
-rw-r--r--os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld31
1 files changed, 19 insertions, 12 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
index 93ed8af3a..39aad4419 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
@@ -109,20 +109,27 @@ SECTIONS
_etext = .;
_textdata = _etext;
- /* Special section for DMA-accessible areas, it is desirable to have a
- separate section of DMA-accessible areas for several reasons:
- - On devices with cache, the whole region can be declared not cacheable
- removing issues with cache consistency.
- - DMA-accessible areas can be placed on a dedicated SRAM bank for
- improved concurrent accesses.*/
- .dma (NOLOAD) : ALIGN(4)
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
{
- *(.dma)
- *(.dma.*)
- *(.bss.__dma_*)
+ __nocache_start__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
. = ALIGN(4);
- __dma_free__ = .;
- } > DMA_RAM
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .ethram (NOLOAD) : ALIGN(4)
+ {
+ __ethram_start__ = .;
+ *(.ethram)
+ *(.ethram.*)
+ *(.bss.__ethram_*)
+ . = ALIGN(4);
+ __ethram_end__ = .;
+ } > ETH_RAM
.mstack :
{