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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:38:16 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:38:16 +0000 |
| commit | 53a30f78fe3e5ebebc379f1f3ab0ef92448ac349 (patch) | |
| tree | 13561be8c59df4b2a6b04ba0f3e57b67fe43d58a /testhal/STM32/STM32F3xx/ADC | |
| parent | d0487d83cf9d96baae56c100ee5f930367756a32 (diff) | |
| download | ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.tar.gz ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.tar.bz2 ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.zip | |
STM32F3 now uses the shared ADCv3 driver. There are differences in the configuration structure.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8599 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32/STM32F3xx/ADC')
| -rw-r--r-- | testhal/STM32/STM32F3xx/ADC/main.c | 4 | ||||
| -rw-r--r-- | testhal/STM32/STM32F3xx/ADC/mcuconf.h | 24 |
2 files changed, 20 insertions, 8 deletions
diff --git a/testhal/STM32/STM32F3xx/ADC/main.c b/testhal/STM32/STM32F3xx/ADC/main.c index 0686becb7..f9b371602 100644 --- a/testhal/STM32/STM32F3xx/ADC/main.c +++ b/testhal/STM32/STM32F3xx/ADC/main.c @@ -59,7 +59,6 @@ static const ADCConversionGroup adcgrpcfg1 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- 0, /* CCR */
{ /* SMPR[2] */
0,
0
@@ -84,7 +83,6 @@ static const ADCConversionGroup adcgrpcfg2 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */
{ /* SMPR[2] */
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
@@ -147,6 +145,8 @@ int main(void) { * Activates the ADC1 driver and the temperature sensor.
*/
adcStart(&ADCD1, NULL);
+ adcSTM32EnableTS(&ADCD1);
+ adcSTM32EnableVBAT(&ADCD1);
/*
* Linear conversion.
diff --git a/testhal/STM32/STM32F3xx/ADC/mcuconf.h b/testhal/STM32/STM32F3xx/ADC/mcuconf.h index afebd01e5..bff0f1d41 100644 --- a/testhal/STM32/STM32F3xx/ADC/mcuconf.h +++ b/testhal/STM32/STM32F3xx/ADC/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 TRUE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
|