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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:38:16 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:38:16 +0000 |
| commit | 53a30f78fe3e5ebebc379f1f3ab0ef92448ac349 (patch) | |
| tree | 13561be8c59df4b2a6b04ba0f3e57b67fe43d58a | |
| parent | d0487d83cf9d96baae56c100ee5f930367756a32 (diff) | |
| download | ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.tar.gz ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.tar.bz2 ChibiOS-53a30f78fe3e5ebebc379f1f3ab0ef92448ac349.zip | |
STM32F3 now uses the shared ADCv3 driver. There are differences in the configuration structure.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8599 35acf78f-673a-0410-8e92-d51de3d6d3f4
27 files changed, 510 insertions, 1323 deletions
diff --git a/demos/STM32/NIL-STM32F303-DISCOVERY/mcuconf.h b/demos/STM32/NIL-STM32F303-DISCOVERY/mcuconf.h index ba950f7a6..e31ab72ea 100644 --- a/demos/STM32/NIL-STM32F303-DISCOVERY/mcuconf.h +++ b/demos/STM32/NIL-STM32F303-DISCOVERY/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h index 7da706298..8560d7306 100644 --- a/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h @@ -62,12 +62,18 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h index ccf47a573..8119e8e77 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/demos/STM32/RT-STM32F303K8-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32F303K8-NUCLEO32/mcuconf.h index e62fbeb8a..b15ca101e 100644 --- a/demos/STM32/RT-STM32F303K8-NUCLEO32/mcuconf.h +++ b/demos/STM32/RT-STM32F303K8-NUCLEO32/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/demos/STM32/RT-STM32F334R8-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F334R8-NUCLEO/mcuconf.h index 7da706298..8560d7306 100644 --- a/demos/STM32/RT-STM32F334R8-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F334R8-NUCLEO/mcuconf.h @@ -62,12 +62,18 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c index ad5d7b220..f186670dd 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c @@ -493,13 +493,13 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
rccEnableADC12(FALSE);
rccResetADC12();
- ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+ ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12(FALSE);
#endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
rccEnableADC34(FALSE);
rccResetADC34();
- ADC3_4_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+ ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34(FALSE);
#endif
#endif
@@ -650,6 +650,9 @@ void adc_lld_stop(ADCDriver *adcp) { adc_lld_analog_off(adcp);
adc_lld_vreg_off(adcp);
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
clkmask &= ~(1 << 0);
@@ -797,10 +800,14 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { * @details The VREFEN bit is required in order to sample the VREF channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32EnableVREF(void) {
+void adcSTM32EnableVREF(ADCDriver *adcp) {
- ADC123_COMMON->CCR |= ADC_CCR_VBATEN;
+ adcp->adcc->CCR |= ADC_CCR_VBATEN;
}
/**
@@ -808,10 +815,14 @@ void adcSTM32EnableVREF(void) { * @details The VREFEN bit is required in order to sample the VREF channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32DisableVREF(void) {
+void adcSTM32DisableVREF(ADCDriver *adcp) {
- ADC123_COMMON->CCR &= ~ADC_CCR_VBATEN;
+ adcp->adcc->CCR &= ~ADC_CCR_VBATEN;
}
/**
@@ -819,10 +830,14 @@ void adcSTM32DisableVREF(void) { * @details The TSEN bit is required in order to sample the internal
* temperature sensor and internal reference voltage.
* @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32EnableTS(void) {
+void adcSTM32EnableTS(ADCDriver *adcp) {
- ADC123_COMMON->CCR |= ADC_CCR_TSEN;
+ adcp->adcc->CCR |= ADC_CCR_TSEN;
}
/**
@@ -830,10 +845,14 @@ void adcSTM32EnableTS(void) { * @details The TSEN bit is required in order to sample the internal
* temperature sensor and internal reference voltage.
* @note This is an STM32-only functionality.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32DisableTS(void) {
+void adcSTM32DisableTS(ADCDriver *adcp) {
- ADC123_COMMON->CCR &= ~ADC_CCR_TSEN;
+ adcp->adcc->CCR &= ~ADC_CCR_TSEN;
}
/**
@@ -841,10 +860,14 @@ void adcSTM32DisableTS(void) { * @details The VBATEN bit is required in order to sample the VBAT channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32EnableVBAT(void) {
+void adcSTM32EnableVBAT(ADCDriver *adcp) {
- ADC123_COMMON->CCR |= ADC_CCR_VBATEN;
+ adcp->adcc->CCR |= ADC_CCR_VBATEN;
}
/**
@@ -852,10 +875,14 @@ void adcSTM32EnableVBAT(void) { * @details The VBATEN bit is required in order to sample the VBAT channel.
* @note This is an STM32-only functionality.
* @note This function is meant to be called after @p adcStart().
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
*/
-void adcSTM32DisableVBAT(void) {
+void adcSTM32DisableVBAT(ADCDriver *adcp) {
- ADC123_COMMON->CCR &= ~ADC_CCR_VBATEN;
+ adcp->adcc->CCR &= ~ADC_CCR_VBATEN;
}
#endif /* HAL_USE_ADC */
diff --git a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h index ffb83dedb..c17a86c7e 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.h @@ -671,6 +671,15 @@ typedef struct { * @brief ADC TR1 register initialization data.
*/
uint32_t tr1;
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
+ /**
+ * @brief ADC CCR register initialization data.
+ * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
+ * driver, keep them to zero.
+ * @note This field is only present in dual mode.
+ */
+ uint32_t ccr;
+#endif
/**
* @brief ADC SMPRx registers initialization data.
*/
@@ -681,13 +690,6 @@ typedef struct { uint32_t sqr[4];
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
/**
- * @brief ADC CCR register initialization data.
- * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
- * driver, keep them to zero.
- * @note This field is only present in dual mode.
- */
- uint32_t ccr;
- /**
* @brief Slave ADC SMPRx registers initialization data.
* @note This field is only present in dual mode.
*/
@@ -869,12 +871,12 @@ extern "C" { void adc_lld_stop(ADCDriver *adcp);
void adc_lld_start_conversion(ADCDriver *adcp);
void adc_lld_stop_conversion(ADCDriver *adcp);
- void adcSTM32EnableVREF(void);
- void adcSTM32DisableVREF(void);
- void adcSTM32EnableTS(void);
- void adcSTM32DisableTS(void);
- void adcSTM32EnableVBAT(void);
- void adcSTM32DisableVBAT(void);
+ void adcSTM32EnableVREF(ADCDriver *adcp);
+ void adcSTM32DisableVREF(ADCDriver *adcp);
+ void adcSTM32EnableTS(ADCDriver *adcp);
+ void adcSTM32DisableTS(ADCDriver *adcp);
+ void adcSTM32EnableVBAT(ADCDriver *adcp);
+ void adcSTM32DisableVBAT(ADCDriver *adcp);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.c b/os/hal/ports/STM32/STM32F3xx/adc_lld.c deleted file mode 100644 index b2685d37c..000000000 --- a/os/hal/ports/STM32/STM32F3xx/adc_lld.c +++ /dev/null @@ -1,573 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F3xx/adc_lld.c
- * @brief STM32F3xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#if STM32_ADC_DUAL_MODE
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type dual mode.*/
-#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA ADC_CCR_MDMA_HWORD
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type dual mode.*/
-#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
-#define ADC_DMA_MDMA ADC_CCR_MDMA_WORD
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-
-#else /* !STM32_ADC_DUAL_MODE */
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type single mode.*/
-#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
-#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type single mode.*/
-#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-#endif /* !STM32_ADC_DUAL_MODE */
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-static const ADCConfig default_config = {
- difsel: 0
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Enables the ADC voltage regulator.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_on(ADCDriver *adcp) {
-
- adcp->adcm->CR = 0; /* RM 12.4.3.*/
- adcp->adcm->CR = ADC_CR_ADVREGEN_0;
-#if STM32_ADC_DUAL_MODE
- adcp->adcs->CR = ADC_CR_ADVREGEN_0;
-#endif
- osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
-}
-
-/**
- * @brief Disables the ADC voltage regulator.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_off(ADCDriver *adcp) {
-
- adcp->adcm->CR = 0; /* RM 12.4.3.*/
- adcp->adcm->CR = ADC_CR_ADVREGEN_1;
-#if STM32_ADC_DUAL_MODE
- adcp->adcs->CR = ADC_CR_ADVREGEN_1;
-#endif
-}
-
-/**
- * @brief Enables the ADC analog circuit.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_on(ADCDriver *adcp) {
-
- adcp->adcm->CR |= ADC_CR_ADEN;
- while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
- ;
-#if STM32_ADC_DUAL_MODE
- adcp->adcs->CR |= ADC_CR_ADEN;
- while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
- ;
-#endif
-}
-
-/**
- * @brief Disables the ADC analog circuit.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_off(ADCDriver *adcp) {
-
- adcp->adcm->CR |= ADC_CR_ADDIS;
- while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
- ;
-#if STM32_ADC_DUAL_MODE
- adcp->adcs->CR |= ADC_CR_ADDIS;
- while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
- ;
-#endif
-}
-
-/**
- * @brief Calibrates and ADC unit.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_calibrate(ADCDriver *adcp) {
-
- osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
- adcp->adcm->CR |= ADC_CR_ADCAL;
- while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
- ;
-#if STM32_ADC_DUAL_MODE
- osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
- adcp->adcs->CR |= ADC_CR_ADCAL;
- while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
- ;
-#endif
-}
-
-/**
- * @brief Stops an ongoing conversion, if any.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- */
-static void adc_lld_stop_adc(ADCDriver *adcp) {
-
- if (adcp->adcm->CR & ADC_CR_ADSTART) {
- adcp->adcm->CR |= ADC_CR_ADSTP;
- while (adcp->adcm->CR & ADC_CR_ADSTP)
- ;
- }
-}
-
-/**
- * @brief ADC DMA ISR service routine.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- * @param[in] flags pre-shifted content of the ISR register
- */
-static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
-
- /* DMA errors handling.*/
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- /* DMA, this could help only if the DMA tries to access an unmapped
- address space or violates alignment rules.*/
- _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
- }
- else {
- /* It is possible that the conversion group has already be reset by the
- ADC error handler, in this case this interrupt is spurious.*/
- if (adcp->grpp != NULL) {
- if ((flags & STM32_DMA_ISR_TCIF) != 0) {
- /* Transfer complete processing.*/
- _adc_isr_full_code(adcp);
- }
- else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
- /* Half transfer processing.*/
- _adc_isr_half_code(adcp);
- }
- }
- }
-}
-
-/**
- * @brief ADC ISR service routine.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- * @param[in] isr content of the ISR register
- */
-static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
-
- /* It could be a spurious interrupt caused by overflows after DMA disabling,
- just ignore it in this case.*/
- if (adcp->grpp != NULL) {
- /* Note, an overflow may occur after the conversion ended before the driver
- is able to stop the ADC, this is why the DMA channel is checked too.*/
- if ((isr & ADC_ISR_OVR) &&
- (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
- /* ADC overflow condition, this could happen only if the DMA is unable
- to read data fast enough.*/
- _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
- }
- if (isr & ADC_ISR_AWD1) {
- /* Analog watchdog error.*/
- _adc_isr_error_code(adcp, ADC_ERR_AWD1);
- }
- if (isr & ADC_ISR_AWD2) {
- /* Analog watchdog error.*/
- _adc_isr_error_code(adcp, ADC_ERR_AWD2);
- }
- if (isr & ADC_ISR_AWD3) {
- /* Analog watchdog error.*/
- _adc_isr_error_code(adcp, ADC_ERR_AWD3);
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief ADC1/ADC2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector88) {
- uint32_t isr;
-
- OSAL_IRQ_PROLOGUE();
-
-#if STM32_ADC_DUAL_MODE
- isr = ADC1->ISR;
- isr |= ADC2->ISR;
- ADC1->ISR = isr;
- ADC2->ISR = isr;
-#else /* !STM32_ADC_DUAL_MODE */
- isr = ADC1->ISR;
- ADC1->ISR = isr;
-#endif /* !STM32_ADC_DUAL_MODE */
-
- adc_lld_serve_interrupt(&ADCD1, isr);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-/**
- * @brief ADC3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorFC) {
- uint32_t isr;
-
- OSAL_IRQ_PROLOGUE();
-
- isr = ADC3->ISR;
- ADC3->ISR = isr;
-
- adc_lld_serve_interrupt(&ADCD3, isr);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#if STM32_ADC_DUAL_MODE
-/**
- * @brief ADC4 interrupt handler (as ADC3 slave).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector134) {
- uint32_t isr;
-
- OSAL_IRQ_PROLOGUE();
-
- isr = ADC4->ISR;
- ADC4->ISR = isr;
-
- adc_lld_serve_interrupt(&ADCD3, isr);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_DUAL_MODE */
-#endif /* STM32_ADC_USE_ADC3 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
- /* Driver initialization.*/
- adcObjectInit(&ADCD1);
-#if defined(ADC1_2_COMMON)
- ADCD1.adcc = ADC1_2_COMMON;
-#else
- ADCD1.adcc = ADC1_COMMON;
-#endif
- ADCD1.adcm = ADC1;
-#if STM32_ADC_DUAL_MODE
- ADCD1.adcs = ADC2;
-#endif
- ADCD1.dmastp = STM32_DMA1_STREAM1;
- ADCD1.dmamode = ADC_DMA_SIZE |
- STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
- STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
- /* Driver initialization.*/
- adcObjectInit(&ADCD3);
-#if defined(ADC3_4_COMMON)
- ADCD3.adcc = ADC3_4_COMMON;
-#else
- ADCD3.adcc = ADC3_COMMON;
-#endif
- ADCD3.adcm = ADC3;
-#if STM32_ADC_DUAL_MODE
- ADCD3.adcs = ADC4;
-#endif
- ADCD3.dmastp = STM32_DMA2_STREAM5;
- ADCD3.dmamode = ADC_DMA_SIZE |
- STM32_DMA_CR_PL(STM32_ADC_ADC34_DMA_PRIORITY) |
- STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
- nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
-#if STM32_ADC_DUAL_MODE
- nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
-#endif
-#endif /* STM32_ADC_USE_ADC3 */
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- /* Handling the default configuration.*/
- if (adcp->config == NULL) {
- adcp->config = &default_config;
- }
-
- /* If in stopped state then enables the ADC and DMA clocks.*/
- if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
- if (&ADCD1 == adcp) {
- bool b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
- (void *)adcp);
- osalDbgAssert(!b, "stream already allocated");
- rccEnableADC12(FALSE);
- }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
- if (&ADCD3 == adcp) {
- bool b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
- (void *)adcp);
- osalDbgAssert(!b, "stream already allocated");
- rccEnableADC34(FALSE);
- }
-#endif /* STM32_ADC_USE_ADC2 */
-
- /* Setting DMA peripheral-side pointer.*/
-#if STM32_ADC_DUAL_MODE
- dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
-#else
- dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
-#endif
-
- /* Clock source setting.*/
- adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
-
- /* Differential channels setting.*/
-#if STM32_ADC_DUAL_MODE
- adcp->adcm->DIFSEL = adcp->config->difsel;
- adcp->adcs->DIFSEL = adcp->config->difsel;
-#else
- adcp->adcm->DIFSEL = adcp->config->difsel;
-#endif
-
- /* Master ADC calibration.*/
- adc_lld_vreg_on(adcp);
- adc_lld_calibrate(adcp);
-
- /* Master ADC enabled here in order to reduce conversions latencies.*/
- adc_lld_analog_on(adcp);
- }
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
- /* If in ready state then disables the ADC clock and analog part.*/
- if (adcp->state == ADC_READY) {
-
- /* Releasing the associated DMA channel.*/
- dmaStreamRelease(adcp->dmastp);
-
- /* Stopping the ongoing conversion, if any.*/
- adc_lld_stop_adc(adcp);
-
- /* Disabling ADC analog circuit and regulator.*/
- adc_lld_analog_off(adcp);
- adc_lld_vreg_off(adcp);
-
-#if STM32_ADC_USE_ADC1
- if (&ADCD1 == adcp)
- rccDisableADC12(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC3
- if (&ADCD3 == adcp)
- rccDisableADC34(FALSE);
-#endif
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t dmamode, ccr, cfgr;
- const ADCConversionGroup *grpp = adcp->grpp;
-
- osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
- "odd number of channels in dual mode");
-
- /* Calculating control registers values.*/
- dmamode = adcp->dmamode;
- ccr = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
- ADC_CCR_MDMA_MASK));
- cfgr = grpp->cfgr | ADC_CFGR_DMAEN;
- if (grpp->circular) {
- dmamode |= STM32_DMA_CR_CIRC;
-#if STM32_ADC_DUAL_MODE
- ccr |= ADC_CCR_DMACFG_CIRCULAR;
-#else
- cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
-#endif
- if (adcp->depth > 1) {
- /* If circular buffer depth > 1, then the half transfer interrupt
- is enabled in order to allow streaming processing.*/
- dmamode |= STM32_DMA_CR_HTIE;
- }
- }
-
- /* DMA setup.*/
- dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-#if STM32_ADC_DUAL_MODE
- dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
- (uint32_t)adcp->depth);
-#else
- dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
- (uint32_t)adcp->depth);
-#endif
- dmaStreamSetMode(adcp->dmastp, dmamode);
- dmaStreamEnable(adcp->dmastp);
-
- /* Configuring the CCR register with the static settings ORed with
- the user-specified settings in the conversion group configuration
- structure.*/
- adcp->adcc->CCR = ccr;
-
- /* ADC setup, if it is defined a callback for the analog watch dog then it
- is enabled.*/
- adcp->adcm->ISR = adcp->adcm->ISR;
- adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1;
- adcp->adcm->TR1 = grpp->tr1;
-#if STM32_ADC_DUAL_MODE
- adcp->adcm->SMPR1 = grpp->smpr[0];
- adcp->adcm->SMPR2 = grpp->smpr[1];
- adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
- adcp->adcm->SQR2 = grpp->sqr[1];
- adcp->adcm->SQR3 = grpp->sqr[2];
- adcp->adcm->SQR4 = grpp->sqr[3];
- adcp->adcs->SMPR1 = grpp->ssmpr[0];
- adcp->adcs->SMPR2 = grpp->ssmpr[1];
- adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
- adcp->adcs->SQR2 = grpp->ssqr[1];
- adcp->adcs->SQR3 = grpp->ssqr[2];
- adcp->adcs->SQR4 = grpp->ssqr[3];
-
-#else /* !STM32_ADC_DUAL_MODE */
- adcp->adcm->SMPR1 = grpp->smpr[0];
- adcp->adcm->SMPR2 = grpp->smpr[1];
- adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
- adcp->adcm->SQR2 = grpp->sqr[1];
- adcp->adcm->SQR3 = grpp->sqr[2];
- adcp->adcm->SQR4 = grpp->sqr[3];
-#endif /* !STM32_ADC_DUAL_MODE */
-
- /* ADC configuration.*/
- adcp->adcm->CFGR = cfgr;
-
- /* Starting conversion.*/
- adcp->adcm->CR |= ADC_CR_ADSTART;
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
- dmaStreamDisable(adcp->dmastp);
- adc_lld_stop_adc(adcp);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.h b/os/hal/ports/STM32/STM32F3xx/adc_lld.h deleted file mode 100644 index 668eb5047..000000000 --- a/os/hal/ports/STM32/STM32F3xx/adc_lld.h +++ /dev/null @@ -1,621 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F3xx/adc_lld.h
- * @brief STM32F3xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
-#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
-#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
-#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
-#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
-#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
-#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
-#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
-#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
-#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
-#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
-#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
-#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
-#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
-#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
-#define ADC_CHANNEL_IN16 16 /**< @brief External analog input 16. */
-#define ADC_CHANNEL_IN17 17 /**< @brief External analog input 17. */
-#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */
-/** @} */
-
-/**
- * @name Sampling rates
- * @{
- */
-#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
-#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */
-#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */
-#define ADC_SMPR_SMP_7P5 3 /**< @brief 20 cycles conversion time. */
-#define ADC_SMPR_SMP_19P5 4 /**< @brief 32 cycles conversion time. */
-#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */
-#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */
-#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */
-/** @} */
-
-/**
- * @name Resolution
- * @{
- */
-#define ADC_CFGR1_RES_12BIT (0 << 3)
-#define ADC_CFGR1_RES_10BIT (1 << 3)
-#define ADC_CFGR1_RES_8BIT (2 << 3)
-#define ADC_CFGR1_RES_6BIT (3 << 3)
-/** @} */
-
-/**
- * @name CFGR register configuration helpers
- * @{
- */
-#define ADC_CFGR_DMACFG_MASK (1 << 1)
-#define ADC_CFGR_DMACFG_ONESHOT (0 << 1)
-#define ADC_CFGR_DMACFG_CIRCULAR (1 << 1)
-
-#define ADC_CFGR_RES_MASK (3 << 3)
-#define ADC_CFGR_RES_12BITS (0 << 3)
-#define ADC_CFGR_RES_10BITS (1 << 3)
-#define ADC_CFGR_RES_8BITS (2 << 3)
-#define ADC_CFGR_RES_6BITS (3 << 3)
-
-#define ADC_CFGR_ALIGN_MASK (1 << 5)
-#define ADC_CFGR_ALIGN_RIGHT (0 << 5)
-#define ADC_CFGR_ALIGN_LEFT (1 << 5)
-
-#define ADC_CFGR_EXTSEL_MASK (15 << 6)
-#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 6)
-
-#define ADC_CFGR_EXTEN_MASK (3 << 10)
-#define ADC_CFGR_EXTEN_DISABLED (0 << 10)
-#define ADC_CFGR_EXTEN_RISING (1 << 10)
-#define ADC_CFGR_EXTEN_FALLING (2 << 10)
-#define ADC_CFGR_EXTEN_BOTH (3 << 10)
-
-#define ADC_CFGR_DISCEN_MASK (1 << 16)
-#define ADC_CFGR_DISCEN_DISABLED (0 << 16)
-#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
-
-#define ADC_CFGR_DISCNUM_MASK (7 << 17)
-#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17)
-
-#define ADC_CFGR_AWD1_DISABLED 0
-#define ADC_CFGR_AWD1_ALL (1 << 23)
-#define ADC_CFGR_AWD1_SINGLE(n) (((n) << 26) | (1 << 23) | (1 << 22))
-/** @} */
-
-/**
- * @name CCR register configuration helpers
- * @{
- */
-#define ADC_CCR_DUAL_MASK (31 << 0)
-#define ADC_CCR_DUAL(n) ((n) << 0)
-#define ADC_CCR_DELAY_MASK (15 << 8)
-#define ADC_CCR_DELAY(n) ((n) << 8)
-#define ADC_CCR_DMACFG_MASK (1 << 13)
-#define ADC_CCR_DMACFG_ONESHOT (0 << 13)
-#define ADC_CCR_DMACFG_CIRCULAR (1 << 13)
-#define ADC_CCR_MDMA_MASK (3 << 14)
-#define ADC_CCR_MDMA_DISABLED (0 << 14)
-#define ADC_CCR_MDMA_WORD (2 << 14)
-#define ADC_CCR_MDMA_HWORD (3 << 14)
-#define ADC_CCR_CKMODE_MASK (3 << 16)
-#define ADC_CCR_CKMODE_ADCCK (0 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16)
-#define ADC_CCR_VREFEN (1 << 22)
-#define ADC_CCR_TSEN (1 << 23)
-#define ADC_CCR_VBATEN (1 << 24)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1 FALSE
-#endif
-
-/**
- * @brief ADC3 driver enable switch.
- * @details If set to @p TRUE the support for ADC3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC3 FALSE
-#endif
-
-/**
- * @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief ADC1/ADC2 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC3/ADC4 interrupt priority level setting.
- */
-#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC1/ADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC3/ADC4 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC1/ADC2 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief ADC3/ADC4 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief Enables the ADC master/slave mode.
- */
-#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_DUAL_MODE FALSE
-#endif
-
-/**
- * @brief Makes the ADC samples type an 8bits one.
- */
-#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
-#define STM32_ADC_COMPACT_SAMPLES FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2
-#error "ADC2 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
-#error "ADC3 not present in the selected device"
-#endif
-
-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC3 && !STM32_HAS_ADC4
-#error "ADC4 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC3 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_USE_ADC3 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC3 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC12_CLOCK STM32_ADC12CLK
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC34_CLOCK STM32_ADC34CLK
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC12_CLOCK > 72000000
-#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if STM32_ADC34_CLOCK > 72000000
-#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ADC sample data type.
- */
-#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
-typedef uint16_t adcsample_t;
-#else
-typedef uint8_t adcsample_t;
-#endif
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief Possible ADC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
- ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
- ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */
- ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */
- ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */
-} adcerror_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note The use of this configuration structure requires knowledge of
- * STM32 ADC cell registers interface, please refer to the STM32
- * reference manual for details.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief ADC CFGR register initialization data.
- * @note The bits DMAEN and DMACFG are enforced internally
- * to the driver, keep them to zero.
- * @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
- * specified in continuous more or if the buffer depth is
- * greater than one.
- */
- uint32_t cfgr;
- /**
- * @brief ADC TR1 register initialization data.
- */
- uint32_t tr1;
- /**
- * @brief ADC CCR register initialization data.
- * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
- * driver, keep them to zero.
- */
- uint32_t ccr;
- /**
- * @brief ADC SMPRx registers initialization data.
- */
- uint32_t smpr[2];
- /**
- * @brief ADC SQRx register initialization data.
- */
- uint32_t sqr[4];
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
- /**
- * @brief Slave ADC SMPRx registers initialization data.
- */
- uint32_t ssmpr[2];
- /**
- * @brief Slave ADC SQRx register initialization data.
- */
- uint32_t ssqr[4];
-#endif /* STM32_ADC_DUAL_MODE */
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief ADC DIFSEL register initialization data.
- */
- uint32_t difsel;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the common ADCx_y registers block.
- */
- ADC_Common_TypeDef *adcc;
- /**
- * @brief Pointer to the master ADCx registers block.
- */
- ADC_TypeDef *adcm;
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
- /**
- * @brief Pointer to the slave ADCx registers block.
- */
- ADC_TypeDef *adcs;
-#endif /* STM32_ADC_DUAL_MODE */
- /**
- * @brief Pointer to associated DMA channel.
- */
- const stm32_dma_stream_t *dmastp;
- /**
- * @brief DMA mode bit mask.
- */
- uint32_t dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Threashold register initializer
- * @{
- */
-#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
-/** @} */
-
-/**
- * @name Sequences building helper macros
- * @{
- */
-/**
- * @brief Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 0)
-
-#define ADC_SQR1_SQ1_N(n) ((n) << 6) /**< @brief 1st channel in seq. */
-#define ADC_SQR1_SQ2_N(n) ((n) << 12) /**< @brief 2nd channel in seq. */
-#define ADC_SQR1_SQ3_N(n) ((n) << 18) /**< @brief 3rd channel in seq. */
-#define ADC_SQR1_SQ4_N(n) ((n) << 24) /**< @brief 4th channel in seq. */
-
-#define ADC_SQR2_SQ5_N(n) ((n) << 0) /**< @brief 5th channel in seq. */
-#define ADC_SQR2_SQ6_N(n) ((n) << 6) /**< @brief 6th channel in seq. */
-#define ADC_SQR2_SQ7_N(n) ((n) << 12) /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n) ((n) << 18) /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n) ((n) << 24) /**< @brief 9th channel in seq. */
-
-#define ADC_SQR3_SQ10_N(n) ((n) << 0) /**< @brief 10th channel in seq.*/
-#define ADC_SQR3_SQ11_N(n) ((n) << 6) /**< @brief 11th channel in seq.*/
-#define ADC_SQR3_SQ12_N(n) ((n) << 12) /**< @brief 12th channel in seq.*/
-#define ADC_SQR3_SQ13_N(n) ((n) << 18) /**< @brief 13th channel in seq.*/
-#define ADC_SQR3_SQ14_N(n) ((n) << 24) /**< @brief 14th channel in seq.*/
-
-#define ADC_SQR4_SQ15_N(n) ((n) << 0) /**< @brief 15th channel in seq.*/
-#define ADC_SQR4_SQ16_N(n) ((n) << 6) /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
-#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
-#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
-#define ADC_SMPR1_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
-#define ADC_SMPR1_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
-#define ADC_SMPR1_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
-#define ADC_SMPR1_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
-#define ADC_SMPR1_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
-#define ADC_SMPR1_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
-
-#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
-#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
-#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
-#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
-#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR2_SMP_AN16(n) ((n) << 18) /**< @brief AN16 sampling time. */
-#define ADC_SMPR2_SMP_AN17(n) ((n) << 21) /**< @brief AN17 sampling time. */
-#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index 5c241cac3..1d6b50dac 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -66,12 +66,18 @@ #elif defined(STM32F302xC)
#define PLATFORM_NAME "STM32F302xC Analog & DSP"
+#elif defined(STM32F302xE)
+#define PLATFORM_NAME "STM32F302xE Analog & DSP"
+
#elif defined(STM32F303x8)
#define PLATFORM_NAME "STM32F303x8 Analog & DSP"
#elif defined(STM32F303xC)
#define PLATFORM_NAME "STM32F303xC Analog & DSP"
+#elif defined(STM32F303xE)
+#define PLATFORM_NAME "STM32F303xE Analog & DSP"
+
#elif defined(STM32F318xx)
#define PLATFORM_NAME "STM32F318xx Analog & DSP"
@@ -84,6 +90,9 @@ #elif defined(STM32F358xx)
#define PLATFORM_NAME "STM32F358xx Analog & DSP"
+#elif defined(STM32F398xx)
+#define PLATFORM_NAME "STM32F398xx Analog & DSP"
+
#else
#error "STM32F3xx device not specified"
#endif
diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 43fff73c7..07d633b10 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -7,7 +7,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
-PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/adc_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
endif
ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c
@@ -55,8 +55,8 @@ endif else
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
@@ -78,6 +78,7 @@ endif # Required include directories
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/STM32F3xx \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 25de802d8..fd1131d16 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -33,6 +33,10 @@ #endif
/*===========================================================================*/
+/* Common features. */
+/*===========================================================================*/
+
+/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
@@ -46,9 +50,30 @@ #if defined(STM32F303xC) || defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
#define STM32_HAS_SDADC1 FALSE
#define STM32_HAS_SDADC2 FALSE
@@ -283,9 +308,30 @@ #if defined(STM32F303xE)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
#define STM32_HAS_SDADC1 FALSE
#define STM32_HAS_SDADC2 FALSE
@@ -533,7 +579,18 @@ #if defined(STM32F303x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -739,6 +796,11 @@ #if defined(STM32F301x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -944,6 +1006,11 @@ #if defined(STM32F302x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -1152,7 +1219,18 @@ #if defined(STM32F302xC)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -1382,7 +1460,18 @@ #if defined(STM32F302xE)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -1621,6 +1710,11 @@ #if defined(STM32F318x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -1825,7 +1919,18 @@ #if defined(STM32F328x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -2028,7 +2133,18 @@ #if defined(STM32F358xC)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -2260,7 +2376,18 @@ #if defined(STM32F334x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -2463,9 +2590,30 @@ #if defined(STM32F398xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC4 TRUE
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC4_DMA_CHN 0x00000000
#define STM32_HAS_SDADC1 FALSE
#define STM32_HAS_SDADC2 FALSE
diff --git a/readme.txt b/readme.txt index 89b6ff12e..e435ea3cc 100644 --- a/readme.txt +++ b/readme.txt @@ -123,6 +123,7 @@ - HAL: Added support for UART4...UART8 to the STM32 UARTv2 UART driver.
- HAL: Added support for UART7 and UART8,LPUART1 to the STM32 UARTv2 serial
driver.
+- HAL: STM32F3xx and STM32L4xx devices now share the same ADCv3 driver.
- HAL: STM32F2xx, STM32F4xx and STM32F7xx devices now share the same ADCv2
and DMAv2 drivers.
- HAL: STM32F0xx and STM32L0xx devices now share the same ADCv1 driver.
@@ -132,6 +133,7 @@ data cache invalidation (F2, F4, F7).
- HAL: New STM32 shared DMAv1 driver supporting channel selection and fixing
the behavior with shared IRQs (F0, L0).
+- HAL: New STM32 ADCv3 driver supporting middle STM32 devices (F3, L4).
- HAL: New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7).
- HAL: New STM32 ADCv1 driver supporting small STM32 devices (F0, L0).
- HAL: Introduced support for TIM21 and TIM22 in STM32 ST driver.
diff --git a/testhal/STM32/STM32F3xx/ADC/main.c b/testhal/STM32/STM32F3xx/ADC/main.c index 0686becb7..f9b371602 100644 --- a/testhal/STM32/STM32F3xx/ADC/main.c +++ b/testhal/STM32/STM32F3xx/ADC/main.c @@ -59,7 +59,6 @@ static const ADCConversionGroup adcgrpcfg1 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- 0, /* CCR */
{ /* SMPR[2] */
0,
0
@@ -84,7 +83,6 @@ static const ADCConversionGroup adcgrpcfg2 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */
{ /* SMPR[2] */
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
@@ -147,6 +145,8 @@ int main(void) { * Activates the ADC1 driver and the temperature sensor.
*/
adcStart(&ADCD1, NULL);
+ adcSTM32EnableTS(&ADCD1);
+ adcSTM32EnableVBAT(&ADCD1);
/*
* Linear conversion.
diff --git a/testhal/STM32/STM32F3xx/ADC/mcuconf.h b/testhal/STM32/STM32F3xx/ADC/mcuconf.h index afebd01e5..bff0f1d41 100644 --- a/testhal/STM32/STM32F3xx/ADC/mcuconf.h +++ b/testhal/STM32/STM32F3xx/ADC/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 TRUE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c index b77e267b2..ee0ca1263 100644 --- a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c +++ b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c @@ -59,7 +59,7 @@ static const ADCConversionGroup adcgrpcfg1 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- ADC_CCR_DUAL(1), /* CCR */
+ ADC_CCR_DUAL_FIELD(1), /* CCR */
{ /* SMPR[2] */
0,
0
@@ -94,7 +94,7 @@ static const ADCConversionGroup adcgrpcfg2 = { adcerrorcallback,
ADC_CFGR_CONT, /* CFGR */
ADC_TR(0, 4095), /* TR1 */
- ADC_CCR_DUAL(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */
+ ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN, /* CCR */
{ /* SMPR[2] */
ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)
| ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),
diff --git a/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h b/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h index f2d5f8042..06afe9f31 100644 --- a/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h +++ b/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE TRUE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 TRUE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE TRUE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/CAN/mcuconf.h b/testhal/STM32/STM32F3xx/CAN/mcuconf.h index 39821a947..19ebed62b 100644 --- a/testhal/STM32/STM32F3xx/CAN/mcuconf.h +++ b/testhal/STM32/STM32F3xx/CAN/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/DAC/mcuconf.h b/testhal/STM32/STM32F3xx/DAC/mcuconf.h index 9e74a5da1..42931a10f 100644 --- a/testhal/STM32/STM32F3xx/DAC/mcuconf.h +++ b/testhal/STM32/STM32F3xx/DAC/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/EXT/mcuconf.h b/testhal/STM32/STM32F3xx/EXT/mcuconf.h index 459ca6ae7..506a4f404 100644 --- a/testhal/STM32/STM32F3xx/EXT/mcuconf.h +++ b/testhal/STM32/STM32F3xx/EXT/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h index 99a7eefe4..adb749237 100644 --- a/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h index 7da84f9ec..85398301b 100644 --- a/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/SPI/mcuconf.h b/testhal/STM32/STM32F3xx/SPI/mcuconf.h index 987d1ff82..3e677d132 100644 --- a/testhal/STM32/STM32F3xx/SPI/mcuconf.h +++ b/testhal/STM32/STM32F3xx/SPI/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/UART/mcuconf.h b/testhal/STM32/STM32F3xx/UART/mcuconf.h index 6927bca1a..b4aac9da6 100644 --- a/testhal/STM32/STM32F3xx/UART/mcuconf.h +++ b/testhal/STM32/STM32F3xx/UART/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h index 87c041048..d57435d1b 100644 --- a/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h +++ b/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h b/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h index 87c041048..d57435d1b 100644 --- a/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h +++ b/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
diff --git a/testhal/STM32/STM32F3xx/WDG/mcuconf.h b/testhal/STM32/STM32F3xx/WDG/mcuconf.h index 304b82a90..67c5a4469 100644 --- a/testhal/STM32/STM32F3xx/WDG/mcuconf.h +++ b/testhal/STM32/STM32F3xx/WDG/mcuconf.h @@ -69,17 +69,29 @@ /*
* ADC driver system settings.
*/
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_PRIORITY 2
-#define STM32_ADC_ADC34_DMA_PRIORITY 2
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
|