STM32F3 now uses the shared ADCv3 driver. There are differences in the configuration structure.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8599 35acf78f-673a-0410-8e92-d51de3d6d3f4

14 files changed, 220 insertions, 76 deletions

diff --git a/testhal/STM32/STM32F3xx/ADC/main.c b/testhal/STM32/STM32F3xx/ADC/main.c
index 0686becb7..f9b371602 100644
--- a/testhal/STM32/STM32F3xx/ADC/main.c
+++ b/testhal/STM32/STM32F3xx/ADC/main.c
@@ -59,7 +59,6 @@ static const ADCConversionGroup adcgrpcfg1 = {
   adcerrorcallback,

   ADC_CFGR_CONT,            /* CFGR    */

   ADC_TR(0, 4095),          /* TR1     */

-  0,                        /* CCR     */

   {                         /* SMPR[2] */

     0,

     0

@@ -84,7 +83,6 @@ static const ADCConversionGroup adcgrpcfg2 = {
   adcerrorcallback,

   ADC_CFGR_CONT,                    /* CFGR    */

   ADC_TR(0, 4095),                  /* TR1     */

-  ADC_CCR_TSEN | ADC_CCR_VBATEN,    /* CCR     */

   {                                 /* SMPR[2] */

     ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)

     | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),

@@ -147,6 +145,8 @@ int main(void) {
    * Activates the ADC1 driver and the temperature sensor.

    */

   adcStart(&ADCD1, NULL);

+  adcSTM32EnableTS(&ADCD1);

+  adcSTM32EnableVBAT(&ADCD1);

 

   /*

    * Linear conversion.

diff --git a/testhal/STM32/STM32F3xx/ADC/mcuconf.h b/testhal/STM32/STM32F3xx/ADC/mcuconf.h
index afebd01e5..bff0f1d41 100644
--- a/testhal/STM32/STM32F3xx/ADC/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/ADC/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  TRUE

+#define STM32_ADC_USE_ADC2                  TRUE

 #define STM32_ADC_USE_ADC3                  TRUE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  TRUE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c
index b77e267b2..ee0ca1263 100644
--- a/testhal/STM32/STM32F3xx/ADC_DUAL/main.c
+++ b/testhal/STM32/STM32F3xx/ADC_DUAL/main.c
@@ -59,7 +59,7 @@ static const ADCConversionGroup adcgrpcfg1 = {
   adcerrorcallback,

   ADC_CFGR_CONT,                                                /* CFGR     */

   ADC_TR(0, 4095),                                              /* TR1      */

-  ADC_CCR_DUAL(1),                                              /* CCR      */

+  ADC_CCR_DUAL_FIELD(1),                                        /* CCR      */

   {                                                             /* SMPR[2]  */

     0,

     0

@@ -94,7 +94,7 @@ static const ADCConversionGroup adcgrpcfg2 = {
   adcerrorcallback,

   ADC_CFGR_CONT,                                                /* CFGR     */

   ADC_TR(0, 4095),                                              /* TR1      */

-  ADC_CCR_DUAL(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN,              /* CCR      */

+  ADC_CCR_DUAL_FIELD(1) | ADC_CCR_TSEN | ADC_CCR_VBATEN,        /* CCR      */

   {                                                             /* SMPR[2]  */

     ADC_SMPR1_SMP_AN7(ADC_SMPR_SMP_19P5)

     | ADC_SMPR1_SMP_AN8(ADC_SMPR_SMP_19P5),

diff --git a/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h b/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h
index f2d5f8042..06afe9f31 100644
--- a/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/ADC_DUAL/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 TRUE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  TRUE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  TRUE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 TRUE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/CAN/mcuconf.h b/testhal/STM32/STM32F3xx/CAN/mcuconf.h
index 39821a947..19ebed62b 100644
--- a/testhal/STM32/STM32F3xx/CAN/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/CAN/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/DAC/mcuconf.h b/testhal/STM32/STM32F3xx/DAC/mcuconf.h
index 9e74a5da1..42931a10f 100644
--- a/testhal/STM32/STM32F3xx/DAC/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/DAC/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/EXT/mcuconf.h b/testhal/STM32/STM32F3xx/EXT/mcuconf.h
index 459ca6ae7..506a4f404 100644
--- a/testhal/STM32/STM32F3xx/EXT/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/EXT/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h
index 99a7eefe4..adb749237 100644
--- a/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/IRQ_STORM/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h
index 7da84f9ec..85398301b 100644
--- a/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/PWM-ICU/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/SPI/mcuconf.h b/testhal/STM32/STM32F3xx/SPI/mcuconf.h
index 987d1ff82..3e677d132 100644
--- a/testhal/STM32/STM32F3xx/SPI/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/SPI/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/UART/mcuconf.h b/testhal/STM32/STM32F3xx/UART/mcuconf.h
index 6927bca1a..b4aac9da6 100644
--- a/testhal/STM32/STM32F3xx/UART/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/UART/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h
index 87c041048..d57435d1b 100644
--- a/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/USB_CDC/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h b/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h
index 87c041048..d57435d1b 100644
--- a/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/USB_CDC_IAD/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.

diff --git a/testhal/STM32/STM32F3xx/WDG/mcuconf.h b/testhal/STM32/STM32F3xx/WDG/mcuconf.h
index 304b82a90..67c5a4469 100644
--- a/testhal/STM32/STM32F3xx/WDG/mcuconf.h
+++ b/testhal/STM32/STM32F3xx/WDG/mcuconf.h
@@ -69,17 +69,29 @@
 /*

  * ADC driver system settings.

  */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_PRIORITY        2

-#define STM32_ADC_ADC34_DMA_PRIORITY        2

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

-#define STM32_ADC_ADC34_IRQ_PRIORITY        5

-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5

-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC_DUAL_MODE                 FALSE

 

 /*

  * CAN driver system settings.