git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8135 35acf78f-673a-0410-8e92-d51de3d6d3f4

16 files changed, 5623 insertions, 1535 deletions

diff --git a/os/ext/CMSIS/include/arm_common_tables.h b/os/ext/CMSIS/include/arm_common_tables.h
index 9c37ab4e5..911ecd49a 100644
--- a/os/ext/CMSIS/include/arm_common_tables.h
+++ b/os/ext/CMSIS/include/arm_common_tables.h
@@ -1,13 +1,13 @@
 /* ----------------------------------------------------------------------

-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.

+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

 *

-* $Date:        17. January 2013

-* $Revision:    V1.4.1

+* $Date:        19. March 2015

+* $Revision: 	V.1.4.5

 *

-* Project:      CMSIS DSP Library

-* Title:        arm_common_tables.h

+* Project: 	    CMSIS DSP Library

+* Title:	    arm_common_tables.h

 *

-* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions

+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions

 *

 * Target Processor: Cortex-M4/Cortex-M3

 *

@@ -46,8 +46,8 @@
 extern const uint16_t armBitRevTable[1024];

 extern const q15_t armRecipTableQ15[64];

 extern const q31_t armRecipTableQ31[64];

-extern const q31_t realCoefAQ31[1024];

-extern const q31_t realCoefBQ31[1024];

+//extern const q31_t realCoefAQ31[1024];

+//extern const q31_t realCoefBQ31[1024];

 extern const float32_t twiddleCoef_16[32];

 extern const float32_t twiddleCoef_32[64];

 extern const float32_t twiddleCoef_64[128];

@@ -58,8 +58,24 @@ extern const float32_t twiddleCoef_1024[2048];
 extern const float32_t twiddleCoef_2048[4096];

 extern const float32_t twiddleCoef_4096[8192];

 #define twiddleCoef twiddleCoef_4096

-extern const q31_t twiddleCoefQ31[6144];

-extern const q15_t twiddleCoefQ15[6144];

+extern const q31_t twiddleCoef_16_q31[24];

+extern const q31_t twiddleCoef_32_q31[48];

+extern const q31_t twiddleCoef_64_q31[96];

+extern const q31_t twiddleCoef_128_q31[192];

+extern const q31_t twiddleCoef_256_q31[384];

+extern const q31_t twiddleCoef_512_q31[768];

+extern const q31_t twiddleCoef_1024_q31[1536];

+extern const q31_t twiddleCoef_2048_q31[3072];

+extern const q31_t twiddleCoef_4096_q31[6144];

+extern const q15_t twiddleCoef_16_q15[24];

+extern const q15_t twiddleCoef_32_q15[48];

+extern const q15_t twiddleCoef_64_q15[96];

+extern const q15_t twiddleCoef_128_q15[192];

+extern const q15_t twiddleCoef_256_q15[384];

+extern const q15_t twiddleCoef_512_q15[768];

+extern const q15_t twiddleCoef_1024_q15[1536];

+extern const q15_t twiddleCoef_2048_q15[3072];

+extern const q15_t twiddleCoef_4096_q15[6144];

 extern const float32_t twiddleCoef_rfft_32[32];

 extern const float32_t twiddleCoef_rfft_64[64];

 extern const float32_t twiddleCoef_rfft_128[128];

@@ -70,6 +86,7 @@ extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];

 

 

+/* floating-point bit reversal tables */

 #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )

 #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )

 #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )

@@ -90,4 +107,30 @@ extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENG
 extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];

 extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];

 

+/* fixed-point bit reversal tables */

+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )

+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )

+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )

+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )

+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )

+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )

+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )

+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)

+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

+

+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];

+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];

+

+/* Tables for Fast Math Sine and Cosine */

+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];

+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];

+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];

+

 #endif /*  ARM_COMMON_TABLES_H */

diff --git a/os/ext/CMSIS/include/arm_const_structs.h b/os/ext/CMSIS/include/arm_const_structs.h
index 406f737dc..54595f55d 100644
--- a/os/ext/CMSIS/include/arm_const_structs.h
+++ b/os/ext/CMSIS/include/arm_const_structs.h
@@ -1,15 +1,15 @@
 /* ----------------------------------------------------------------------

-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.

+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

 *

-* $Date:        17. January 2013

-* $Revision:    V1.4.1

+* $Date:        19. March 2015

+* $Revision: 	V.1.4.5

 *

-* Project:      CMSIS DSP Library

-* Title:        arm_const_structs.h

+* Project: 	    CMSIS DSP Library

+* Title:	    arm_const_structs.h

 *

-* Description:  This file has constant structs that are initialized for

-*               user convenience.  For example, some can be given as

-*               arguments to the arm_cfft_f32() function.

+* Description:	This file has constant structs that are initialized for

+*              user convenience.  For example, some can be given as

+*              arguments to the arm_cfft_f32() function.

 *

 * Target Processor: Cortex-M4/Cortex-M3

 *

@@ -46,40 +46,34 @@
 #include "arm_math.h"

 #include "arm_common_tables.h"

 

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {

-      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH

-   };

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;

+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;

 

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {

-      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH

-   };

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;

+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;

 

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {

-      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {

-      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {

-      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {

-      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {

-      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {

-      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH

-   };

-

-   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {

-      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH

-   };

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;

+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;

 

 #endif

diff --git a/os/ext/CMSIS/include/arm_math.h b/os/ext/CMSIS/include/arm_math.h
index 59662ae1a..6dd430dd8 100644
--- a/os/ext/CMSIS/include/arm_math.h
+++ b/os/ext/CMSIS/include/arm_math.h
@@ -1,15 +1,15 @@
 /* ----------------------------------------------------------------------

-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.

+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.

 *

-* $Date:        17. January 2013

-* $Revision:    V1.4.1

+* $Date:        19. March 2015

+* $Revision: 	V.1.4.5

 *

-* Project:      CMSIS DSP Library

-* Title:        arm_math.h

+* Project: 	    CMSIS DSP Library

+* Title:	    arm_math.h

 *

-* Description:  Public header file for CMSIS DSP Library

+* Description:	Public header file for CMSIS DSP Library

 *

-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0

+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

@@ -41,7 +41,8 @@
 /**

    \mainpage CMSIS DSP Software Library

    *

-   * <b>Introduction</b>

+   * Introduction

+   * ------------

    *

    * This user manual describes the CMSIS DSP software library,

    * a suite of common signal processing functions for use on Cortex-M processor based devices.

@@ -61,49 +62,53 @@
    * The library has separate functions for operating on 8-bit integers, 16-bit integers,

    * 32-bit integer and 32-bit floating-point values.

    *

-   * <b>Using the Library</b>

+   * Using the Library

+   * ------------

    *

    * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.

+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)

+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)

+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)

+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)

+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)

+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)

    * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)

    * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)

    * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)

    * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)

    * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)

    * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)

-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)

-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)

+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)

+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)

    *

    * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.

    * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single

-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.

-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or

+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.

+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or

    * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.

    *

-   * <b>Examples</b>

+   * Examples

+   * --------

    *

    * The library ships with a number of examples which demonstrate how to use the library functions.

    *

-   * <b>Toolchain Support</b>

+   * Toolchain Support

+   * ------------

    *

-   * The library has been developed and tested with MDK-ARM version 4.60.

+   * The library has been developed and tested with MDK-ARM version 5.14.0.0

    * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

    *

-   * <b>Building the Library</b>

+   * Building the Library

+   * ------------

    *

-   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.

-   * - arm_cortexM0b_math.uvproj

-   * - arm_cortexM0l_math.uvproj

-   * - arm_cortexM3b_math.uvproj

-   * - arm_cortexM3l_math.uvproj

-   * - arm_cortexM4b_math.uvproj

-   * - arm_cortexM4l_math.uvproj

-   * - arm_cortexM4bf_math.uvproj

-   * - arm_cortexM4lf_math.uvproj

+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.

+   * - arm_cortexM_math.uvprojx

    *

    *

-   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.

+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.

    *

-   * <b>Pre-processor Macros</b>

+   * Pre-processor Macros

+   * ------------

    *

    * Each library project have differant pre-processor macros.

    *

@@ -126,15 +131,34 @@
    * - ARM_MATH_CMx:

    *

    * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target

-   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.

+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and

+   * ARM_MATH_CM7 for building the library on cortex-M7.

    *

    * - __FPU_PRESENT:

    *

    * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

    *

-   * <b>Copyright Notice</b>

+   * <hr>

+   * CMSIS-DSP in ARM::CMSIS Pack

+   * -----------------------------

+   * 

+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:

+   * |File/Folder                   |Content                                                                 |

+   * |------------------------------|------------------------------------------------------------------------|

+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |

+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |

+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |

+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |

+   * 

+   * <hr>

+   * Revision History of CMSIS-DSP

+   * ------------

+   * Please refer to \ref ChangeLog_pg.

    *

-   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.

+   * Copyright Notice

+   * ------------

+   *

+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.

    */

 

 

@@ -266,19 +290,20 @@
 

 #define __CMSIS_GENERIC         /* disable NVIC and Systick functions */

 

-#if defined (ARM_MATH_CM4)

-#include "core_cm4.h"

+#if defined(ARM_MATH_CM7)

+  #include "core_cm7.h"

+#elif defined (ARM_MATH_CM4)

+  #include "core_cm4.h"

 #elif defined (ARM_MATH_CM3)

-#include "core_cm3.h"

+  #include "core_cm3.h"

 #elif defined (ARM_MATH_CM0)

-#include "core_cm0.h"

+  #include "core_cm0.h"

 #define ARM_MATH_CM0_FAMILY

-#elif defined (ARM_MATH_CM0PLUS)

+  #elif defined (ARM_MATH_CM0PLUS)

 #include "core_cm0plus.h"

-#define ARM_MATH_CM0_FAMILY

+  #define ARM_MATH_CM0_FAMILY

 #else

-#include "ARMCM4.h"

-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."

+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"

 #endif

 

 #undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */

@@ -305,9 +330,13 @@ extern "C"
    * @brief Macros required for SINE and COSINE Fast math approximations

    */

 

-#define TABLE_SIZE			256

-#define TABLE_SPACING_Q31	0x800000

-#define TABLE_SPACING_Q15	0x80

+#define FAST_MATH_TABLE_SIZE  512

+#define FAST_MATH_Q31_SHIFT   (32 - 10)

+#define FAST_MATH_Q15_SHIFT   (16 - 10)

+#define CONTROLLER_Q31_SHIFT  (32 - 9)

+#define TABLE_SIZE  256

+#define TABLE_SPACING_Q31	   0x400000

+#define TABLE_SPACING_Q15	   0x80

 

   /**

    * @brief Macros required for SINE and COSINE Controller functions

@@ -378,16 +407,22 @@ extern "C"
    * @brief definition to read/write two 16 bit values.

    */

 #if defined __CC_ARM

-#define __SIMD32_TYPE int32_t __packed

-#define CMSIS_UNUSED __attribute__((unused))

+  #define __SIMD32_TYPE int32_t __packed

+  #define CMSIS_UNUSED __attribute__((unused))

 #elif defined __ICCARM__

-#define CMSIS_UNUSED

-#define __SIMD32_TYPE int32_t __packed

+  #define __SIMD32_TYPE int32_t __packed

+  #define CMSIS_UNUSED

 #elif defined __GNUC__

-#define __SIMD32_TYPE int32_t

-#define CMSIS_UNUSED __attribute__((unused))

+  #define __SIMD32_TYPE int32_t

+  #define CMSIS_UNUSED __attribute__((unused))

+#elif defined __CSMC__			/* Cosmic */

+  #define __SIMD32_TYPE int32_t

+  #define CMSIS_UNUSED

+#elif defined __TASKING__

+  #define __SIMD32_TYPE __unaligned int32_t

+  #define CMSIS_UNUSED

 #else

-#error Unknown compiler

+  #error Unknown compiler

 #endif

 

 #define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))

@@ -481,11 +516,12 @@ extern "C"
   }

 

 

-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )

-#define __CLZ __clz

-#endif

+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )

+//#define __CLZ __clz

+//#endif

 

-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )

+//note: function can be removed when all toolchain support __CLZ for Cortex-M0

+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )

 

   static __INLINE uint32_t __CLZ(

   q31_t data);

@@ -730,8 +766,8 @@ extern "C"
     q31_t sum;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = __SSAT(r + s, 16);

     s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;

@@ -753,8 +789,8 @@ extern "C"
     q31_t sum;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = ((r >> 1) + (s >> 1));

     s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;

@@ -776,8 +812,8 @@ extern "C"
     q31_t sum;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = __SSAT(r - s, 16);

     s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;

@@ -798,8 +834,8 @@ extern "C"
     q31_t diff;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = ((r >> 1) - (s >> 1));

     s = (((x >> 17) - (y >> 17)) << 16);

@@ -821,8 +857,8 @@ extern "C"
 

     sum =

       ((sum +

-        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +

-      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));

+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +

+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));

 

     return sum;

   }

@@ -838,8 +874,8 @@ extern "C"
     q31_t sum;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = ((r >> 1) - (y >> 17));

     s = (((x >> 17) + (s >> 1)) << 16);

@@ -862,8 +898,8 @@ extern "C"
 

     sum =

       ((sum +

-        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +

-      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));

+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +

+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));

 

     return sum;

   }

@@ -879,8 +915,8 @@ extern "C"
     q31_t sum;

     q31_t r, s;

 

-    r = (short) x;

-    s = (short) y;

+    r = (q15_t) x;

+    s = (q15_t) y;

 

     r = ((r >> 1) + (y >> 17));

     s = (((x >> 17) - (s >> 1)) << 16);

@@ -898,8 +934,8 @@ extern "C"
   q31_t y)

   {

 

-    return ((q31_t) (((short) x * (short) (y >> 16)) -

-                     ((short) (x >> 16) * (short) y)));

+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -

+                     ((q15_t) (x >> 16) * (q15_t) y)));

   }

 

   /*

@@ -910,8 +946,8 @@ extern "C"
   q31_t y)

   {

 

-    return ((q31_t) (((short) x * (short) (y >> 16)) +

-                     ((short) (x >> 16) * (short) y)));

+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +

+                     ((q15_t) (x >> 16) * (q15_t) y)));

   }

 

   /*

@@ -943,8 +979,8 @@ extern "C"
   q31_t sum)

   {

 

-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +

-            ((short) x * (short) y));

+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +

+            ((q15_t) x * (q15_t) y));

   }

 

   /*

@@ -956,8 +992,8 @@ extern "C"
   q31_t sum)

   {

 

-    return (sum + ((short) (x >> 16) * (short) (y)) +

-            ((short) x * (short) (y >> 16)));

+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +

+            ((q15_t) x * (q15_t) (y >> 16)));

   }

 

   /*

@@ -969,8 +1005,8 @@ extern "C"
   q31_t sum)

   {

 

-    return (sum - ((short) (x >> 16) * (short) (y)) +

-            ((short) x * (short) (y >> 16)));

+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +

+            ((q15_t) x * (q15_t) (y >> 16)));

   }

 

   /*

@@ -982,8 +1018,8 @@ extern "C"
   q63_t sum)

   {

 

-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +

-            ((short) x * (short) y));

+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +

+            ((q15_t) x * (q15_t) y));

   }

 

   /*

@@ -995,8 +1031,8 @@ extern "C"
   q63_t sum)

   {

 

-    return (sum + ((short) (x >> 16) * (short) y)) +

-      ((short) x * (short) (y >> 16));

+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +

+      ((q15_t) x * (q15_t) (y >> 16));

   }

 

   /*

@@ -1410,6 +1446,18 @@ extern "C"
     float32_t *pData;     /**< points to the data of the matrix. */

   } arm_matrix_instance_f32;

 

+

+  /**

+   * @brief Instance structure for the floating-point matrix structure.

+   */

+

+  typedef struct

+  {

+    uint16_t numRows;     /**< number of rows of the matrix.     */

+    uint16_t numCols;     /**< number of columns of the matrix.  */

+    float64_t *pData;     /**< points to the data of the matrix. */

+  } arm_matrix_instance_f64;

+

   /**

    * @brief Instance structure for the Q15 matrix structure.

    */

@@ -1478,6 +1526,49 @@ extern "C"
   const arm_matrix_instance_q31 * pSrcB,

   arm_matrix_instance_q31 * pDst);

 

+  /**

+   * @brief Floating-point, complex, matrix multiplication.

+   * @param[in]       *pSrcA points to the first input matrix structure

+   * @param[in]       *pSrcB points to the second input matrix structure

+   * @param[out]      *pDst points to output matrix structure

+   * @return     The function returns either

+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

+   */

+

+  arm_status arm_mat_cmplx_mult_f32(

+  const arm_matrix_instance_f32 * pSrcA,

+  const arm_matrix_instance_f32 * pSrcB,

+  arm_matrix_instance_f32 * pDst);

+

+  /**

+   * @brief Q15, complex,  matrix multiplication.

+   * @param[in]       *pSrcA points to the first input matrix structure

+   * @param[in]       *pSrcB points to the second input matrix structure

+   * @param[out]      *pDst points to output matrix structure

+   * @return     The function returns either

+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

+   */

+

+  arm_status arm_mat_cmplx_mult_q15(

+  const arm_matrix_instance_q15 * pSrcA,

+  const arm_matrix_instance_q15 * pSrcB,

+  arm_matrix_instance_q15 * pDst,

+  q15_t * pScratch);

+

+  /**

+   * @brief Q31, complex, matrix multiplication.

+   * @param[in]       *pSrcA points to the first input matrix structure

+   * @param[in]       *pSrcB points to the second input matrix structure

+   * @param[out]      *pDst points to output matrix structure

+   * @return     The function returns either

+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

+   */

+

+  arm_status arm_mat_cmplx_mult_q31(

+  const arm_matrix_instance_q31 * pSrcA,

+  const arm_matrix_instance_q31 * pSrcB,

+  arm_matrix_instance_q31 * pDst);

+

 

   /**

    * @brief Floating-point matrix transpose.

@@ -1536,7 +1627,7 @@ extern "C"
    * @param[in]       *pSrcA points to the first input matrix structure

    * @param[in]       *pSrcB points to the second input matrix structure

    * @param[out]      *pDst points to output matrix structure

-   * @param[in]		  *pState points to the array for storing intermediate results

+   * @param[in]		 *pState points to the array for storing intermediate results

    * @return     The function returns either

    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

    */

@@ -1971,12 +2062,14 @@ extern "C"
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

   } arm_cfft_radix2_instance_q15;

 

+/* Deprecated */

   arm_status arm_cfft_radix2_init_q15(

   arm_cfft_radix2_instance_q15 * S,

   uint16_t fftLen,

   uint8_t ifftFlag,

   uint8_t bitReverseFlag);

 

+/* Deprecated */

   void arm_cfft_radix2_q15(

   const arm_cfft_radix2_instance_q15 * S,

   q15_t * pSrc);

@@ -1998,12 +2091,14 @@ extern "C"
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

   } arm_cfft_radix4_instance_q15;

 

+/* Deprecated */

   arm_status arm_cfft_radix4_init_q15(

   arm_cfft_radix4_instance_q15 * S,

   uint16_t fftLen,

   uint8_t ifftFlag,

   uint8_t bitReverseFlag);

 

+/* Deprecated */

   void arm_cfft_radix4_q15(

   const arm_cfft_radix4_instance_q15 * S,

   q15_t * pSrc);

@@ -2023,12 +2118,14 @@ extern "C"
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

   } arm_cfft_radix2_instance_q31;

 

+/* Deprecated */

   arm_status arm_cfft_radix2_init_q31(

   arm_cfft_radix2_instance_q31 * S,

   uint16_t fftLen,

   uint8_t ifftFlag,

   uint8_t bitReverseFlag);

 

+/* Deprecated */

   void arm_cfft_radix2_q31(

   const arm_cfft_radix2_instance_q31 * S,

   q31_t * pSrc);

@@ -2048,11 +2145,12 @@ extern "C"
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

   } arm_cfft_radix4_instance_q31;

 

-

+/* Deprecated */

   void arm_cfft_radix4_q31(

   const arm_cfft_radix4_instance_q31 * S,

   q31_t * pSrc);

 

+/* Deprecated */

   arm_status arm_cfft_radix4_init_q31(

   arm_cfft_radix4_instance_q31 * S,

   uint16_t fftLen,

@@ -2116,6 +2214,42 @@ extern "C"
   float32_t * pSrc);

 

   /**

+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

+   */

+

+  typedef struct

+  {

+    uint16_t fftLen;                   /**< length of the FFT. */

+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */

+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

+    uint16_t bitRevLength;             /**< bit reversal table length. */

+  } arm_cfft_instance_q15;

+

+void arm_cfft_q15( 

+    const arm_cfft_instance_q15 * S, 

+    q15_t * p1,

+    uint8_t ifftFlag,

+    uint8_t bitReverseFlag);  

+

+  /**

+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

+   */

+

+  typedef struct

+  {

+    uint16_t fftLen;                   /**< length of the FFT. */

+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */

+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

+    uint16_t bitRevLength;             /**< bit reversal table length. */

+  } arm_cfft_instance_q31;

+

+void arm_cfft_q31( 

+    const arm_cfft_instance_q31 * S, 

+    q31_t * p1,

+    uint8_t ifftFlag,

+    uint8_t bitReverseFlag);  

+  

+  /**

    * @brief Instance structure for the floating-point CFFT/CIFFT function.

    */

 

@@ -2140,18 +2274,16 @@ extern "C"
   typedef struct

   {

     uint32_t fftLenReal;                      /**< length of the real FFT. */

-    uint32_t fftLenBy2;                       /**< length of the complex FFT. */

     uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

     uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

     q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */

     q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */

-    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */

+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */

   } arm_rfft_instance_q15;

 

   arm_status arm_rfft_init_q15(

   arm_rfft_instance_q15 * S,

-  arm_cfft_radix4_instance_q15 * S_CFFT,

   uint32_t fftLenReal,

   uint32_t ifftFlagR,

   uint32_t bitReverseFlag);

@@ -2168,18 +2300,16 @@ extern "C"
   typedef struct

   {

     uint32_t fftLenReal;                        /**< length of the real FFT. */

-    uint32_t fftLenBy2;                         /**< length of the complex FFT. */

     uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

     uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

     q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */

     q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */

-    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */

+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */

   } arm_rfft_instance_q31;

 

   arm_status arm_rfft_init_q31(

   arm_rfft_instance_q31 * S,

-  arm_cfft_radix4_instance_q31 * S_CFFT,

   uint32_t fftLenReal,

   uint32_t ifftFlagR,

   uint32_t bitReverseFlag);

@@ -3694,6 +3824,32 @@ void arm_rfft_fast_f32(
   } arm_biquad_cascade_df2T_instance_f32;

 

 

+

+  /**

+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

+   */

+

+  typedef struct

+  {

+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */

+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

+  } arm_biquad_cascade_stereo_df2T_instance_f32;

+

+

+

+  /**

+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

+   */

+

+  typedef struct

+  {

+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */

+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

+  } arm_biquad_cascade_df2T_instance_f64;

+

+

   /**

    * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

    * @param[in]  *S        points to an instance of the filter data structure.

@@ -3711,6 +3867,37 @@ void arm_rfft_fast_f32(
 

 

   /**

+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels

+   * @param[in]  *S        points to an instance of the filter data structure.

+   * @param[in]  *pSrc     points to the block of input data.

+   * @param[out] *pDst     points to the block of output data

+   * @param[in]  blockSize number of samples to process.

+   * @return none.

+   */

+

+  void arm_biquad_cascade_stereo_df2T_f32(

+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,

+  float32_t * pSrc,

+  float32_t * pDst,

+  uint32_t blockSize);

+

+  /**

+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

+   * @param[in]  *S        points to an instance of the filter data structure.

+   * @param[in]  *pSrc     points to the block of input data.

+   * @param[out] *pDst     points to the block of output data

+   * @param[in]  blockSize number of samples to process.

+   * @return none.

+   */

+

+  void arm_biquad_cascade_df2T_f64(

+  const arm_biquad_cascade_df2T_instance_f64 * S,

+  float64_t * pSrc,

+  float64_t * pDst,

+  uint32_t blockSize);

+

+

+  /**

    * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

    * @param[in,out] *S           points to an instance of the filter data structure.

    * @param[in]     numStages    number of 2nd order stages in the filter.

@@ -3726,6 +3913,38 @@ void arm_rfft_fast_f32(
   float32_t * pState);

 

 

+  /**

+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

+   * @param[in,out] *S           points to an instance of the filter data structure.

+   * @param[in]     numStages    number of 2nd order stages in the filter.

+   * @param[in]     *pCoeffs     points to the filter coefficients.

+   * @param[in]     *pState      points to the state buffer.

+   * @return        none

+   */

+

+  void arm_biquad_cascade_stereo_df2T_init_f32(

+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,

+  uint8_t numStages,

+  float32_t * pCoeffs,

+  float32_t * pState);

+

+

+  /**

+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

+   * @param[in,out] *S           points to an instance of the filter data structure.

+   * @param[in]     numStages    number of 2nd order stages in the filter.

+   * @param[in]     *pCoeffs     points to the filter coefficients.

+   * @param[in]     *pState      points to the state buffer.

+   * @return        none

+   */

+

+  void arm_biquad_cascade_df2T_init_f64(

+  arm_biquad_cascade_df2T_instance_f64 * S,

+  uint8_t numStages,

+  float64_t * pCoeffs,

+  float64_t * pState);

+

+

 

   /**

    * @brief Instance structure for the Q15 FIR lattice filter.

@@ -5023,6 +5242,19 @@ void arm_rfft_fast_f32(
   arm_matrix_instance_f32 * dst);

 

 

+  /**

+   * @brief Floating-point matrix inverse.

+   * @param[in]  *src points to the instance of the input floating-point matrix structure.

+   * @param[out] *dst points to the instance of the output floating-point matrix structure.

+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.

+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.

+   */

+

+  arm_status arm_mat_inverse_f64(

+  const arm_matrix_instance_f64 * src,

+  arm_matrix_instance_f64 * dst);

+

+

 

   /**

    * @ingroup groupController

@@ -5869,7 +6101,7 @@ void arm_rfft_fast_f32(
   float32_t in,

   float32_t * pOut)

   {

-    if(in > 0)

+    if(in >= 0.0f)

     {

 

 //      #if __FPU_USED

@@ -6350,7 +6582,7 @@ void arm_rfft_fast_f32(
   void arm_var_q31(

   q31_t * pSrc,

   uint32_t blockSize,

-  q63_t * pResult);

+  q31_t * pResult);

 

   /**

    * @brief  Variance of the elements of a Q15 vector.

@@ -6363,7 +6595,7 @@ void arm_rfft_fast_f32(
   void arm_var_q15(

   q15_t * pSrc,

   uint32_t blockSize,

-  q31_t * pResult);

+  q15_t * pResult);

 

   /**

    * @brief  Root Mean Square of the elements of a floating-point vector.

@@ -7208,29 +7440,51 @@ void arm_rfft_fast_f32(
   /**

    * @} end of BilinearInterpolate group

    */

+   

 

-

-#if   defined ( __CC_ARM ) //Keil

 //SMMLAR

-  #define multAcc_32x32_keep32_R(a, x, y) \

-  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)

+#define multAcc_32x32_keep32_R(a, x, y) \

+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)

 

 //SMMLSR

-  #define multSub_32x32_keep32_R(a, x, y) \

-  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)

+#define multSub_32x32_keep32_R(a, x, y) \

+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)

 

 //SMMULR

-  #define mult_32x32_keep32_R(a, x, y) \

-  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)

+#define mult_32x32_keep32_R(a, x, y) \

+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)

+

+//SMMLA

+#define multAcc_32x32_keep32(a, x, y) \

+    a += (q31_t) (((q63_t) x * y) >> 32)

+

+//SMMLS

+#define multSub_32x32_keep32(a, x, y) \

+    a -= (q31_t) (((q63_t) x * y) >> 32)

+

+//SMMUL

+#define mult_32x32_keep32(a, x, y) \

+    a = (q31_t) (((q63_t) x * y ) >> 32)

+

+

+#if defined ( __CC_ARM ) //Keil

 

 //Enter low optimization region - place directly above function definition

-  #define LOW_OPTIMIZATION_ENTER \

-     _Pragma ("push")         \

-     _Pragma ("O1")

+    #ifdef ARM_MATH_CM4

+      #define LOW_OPTIMIZATION_ENTER \

+         _Pragma ("push")         \

+         _Pragma ("O1")

+    #else

+      #define LOW_OPTIMIZATION_ENTER 

+    #endif

 

 //Exit low optimization region - place directly after end of function definition

-  #define LOW_OPTIMIZATION_EXIT \

-     _Pragma ("pop")

+    #ifdef ARM_MATH_CM4

+      #define LOW_OPTIMIZATION_EXIT \

+         _Pragma ("pop")

+    #else

+      #define LOW_OPTIMIZATION_EXIT  

+    #endif

 

 //Enter low optimization region - place directly above function definition

   #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

@@ -7239,44 +7493,30 @@ void arm_rfft_fast_f32(
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

 

 #elif defined(__ICCARM__) //IAR

- //SMMLA

-  #define multAcc_32x32_keep32_R(a, x, y) \

-  a += (q31_t) (((q63_t) x * y) >> 32)

-

- //SMMLS

-  #define multSub_32x32_keep32_R(a, x, y) \

-  a -= (q31_t) (((q63_t) x * y) >> 32)

-

-//SMMUL

-  #define mult_32x32_keep32_R(a, x, y) \

-  a = (q31_t) (((q63_t) x * y ) >> 32)

 

 //Enter low optimization region - place directly above function definition

-  #define LOW_OPTIMIZATION_ENTER \

-     _Pragma ("optimize=low")

+    #ifdef ARM_MATH_CM4

+      #define LOW_OPTIMIZATION_ENTER \

+         _Pragma ("optimize=low")

+    #else

+      #define LOW_OPTIMIZATION_ENTER   

+    #endif

 

 //Exit low optimization region - place directly after end of function definition

   #define LOW_OPTIMIZATION_EXIT

 

 //Enter low optimization region - place directly above function definition

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \

-     _Pragma ("optimize=low")

+    #ifdef ARM_MATH_CM4

+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \

+         _Pragma ("optimize=low")

+    #else

+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   

+    #endif

 

 //Exit low optimization region - place directly after end of function definition

   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

 

 #elif defined(__GNUC__)

- //SMMLA

-  #define multAcc_32x32_keep32_R(a, x, y) \

-  a += (q31_t) (((q63_t) x * y) >> 32)

-

- //SMMLS

-  #define multSub_32x32_keep32_R(a, x, y) \

-  a -= (q31_t) (((q63_t) x * y) >> 32)

-

-//SMMUL

-  #define mult_32x32_keep32_R(a, x, y) \

-  a = (q31_t) (((q63_t) x * y ) >> 32)

 

   #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))

 

@@ -7286,10 +7526,21 @@ void arm_rfft_fast_f32(
 

   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

 

-#endif

+#elif defined(__CSMC__)		// Cosmic

 

+#define LOW_OPTIMIZATION_ENTER

+#define LOW_OPTIMIZATION_EXIT

+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER

+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

 

+#elif defined(__TASKING__)		// TASKING

 

+#define LOW_OPTIMIZATION_ENTER

+#define LOW_OPTIMIZATION_EXIT

+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER

+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

+

+#endif

 

 

 #ifdef	__cplusplus

@@ -7299,7 +7550,6 @@ void arm_rfft_fast_f32(
 

 #endif /* _ARM_MATH_H */

 

-

 /**

  *

  * End of file.

diff --git a/os/ext/CMSIS/include/core_cm0.h b/os/ext/CMSIS/include/core_cm0.h
index 1b6b54ef4..1110d17a3 100644
--- a/os/ext/CMSIS/include/core_cm0.h
+++ b/os/ext/CMSIS/include/core_cm0.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cm0.h

  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2015 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -39,13 +39,13 @@
  #pragma system_include  /* treat file as system include file for MISRA check */

 #endif

 

+#ifndef __CORE_CM0_H_GENERIC

+#define __CORE_CM0_H_GENERIC

+

 #ifdef __cplusplus

  extern "C" {

 #endif

 

-#ifndef __CORE_CM0_H_GENERIC

-#define __CORE_CM0_H_GENERIC

-

 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

   CMSIS violates the following MISRA-C:2004 rules:

 

@@ -68,8 +68,8 @@
  */

 

 /*  CMSIS CM0 definitions */

-#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \

                                     __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

 

@@ -81,14 +81,18 @@
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

   #define __STATIC_INLINE  static __inline

 

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

 #elif defined ( __ICCARM__ )

   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

   #define __STATIC_INLINE  static inline

 

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

   #define __STATIC_INLINE  static inline

 

 #elif defined ( __TASKING__ )

@@ -96,9 +100,16 @@
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

   #define __STATIC_INLINE  static inline

 

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

 #endif

 

-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

 */

 #define __FPU_USED       0

 

@@ -107,13 +118,18 @@
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

 #elif defined ( __ICCARM__ )

   #if defined __ARMVFP__

     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+#elif defined ( __TMS470__ )

+  #if defined __TI__VFP_SUPPORT____

     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

@@ -121,12 +137,21 @@
   #if defined __FPU_VFP__

     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

 #endif

 

 #include <stdint.h>                      /* standard types definitions                      */

 #include <core_cmInstr.h>                /* Core Instruction Access                         */

 #include <core_cmFunc.h>                 /* Core Function Access                            */

 

+#ifdef __cplusplus

+}

+#endif

+

 #endif /* __CORE_CM0_H_GENERIC */

 

 #ifndef __CMSIS_GENERIC

@@ -134,6 +159,10 @@
 #ifndef __CORE_CM0_H_DEPENDANT

 #define __CORE_CM0_H_DEPENDANT

 

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

 /* check device defines and use defaults */

 #if defined __CHECK_DEVICE_DEFINES

   #ifndef __CM0_REV

@@ -196,14 +225,7 @@ typedef union
 {

   struct

   {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

@@ -212,6 +234,19 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } APSR_Type;

 

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

 

 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).

  */

@@ -225,6 +260,10 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } IPSR_Type;

 

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

  */

@@ -233,16 +272,9 @@ typedef union
   struct

   {

     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

@@ -251,6 +283,25 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } xPSR_Type;

 

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Control Registers (CONTROL).

  */

@@ -258,14 +309,17 @@ typedef union
 {

   struct

   {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */

     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

   } b;                                   /*!< Structure used for bit  access                  */

   uint32_t w;                            /*!< Type      used for word access                  */

 } CONTROL_Type;

 

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

 /*@} end of group CMSIS_CORE */

 

 

@@ -329,7 +383,7 @@ typedef struct
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

 

 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

 

 /* SCB Interrupt Control State Register Definitions */

 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

@@ -357,7 +411,7 @@ typedef struct
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

 

 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

 

 /* SCB Application Interrupt and Reset Control Register Definitions */

 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

@@ -426,15 +480,15 @@ typedef struct
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

 

 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

 

 /* SysTick Reload Register Definitions */

 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

 

 /* SysTick Current Register Definitions */

 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

 

 /* SysTick Calibration Register Definitions */

 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

@@ -444,7 +498,7 @@ typedef struct
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

 

 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

 

 /*@} end of group CMSIS_SysTick */

 

@@ -501,9 +555,9 @@ typedef struct
 

 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */

 /* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

 

 

 /** \brief  Enable External Interrupt

@@ -514,7 +568,7 @@ typedef struct
  */

 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -526,7 +580,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -542,7 +596,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

 {

-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -554,7 +608,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -566,7 +620,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -581,12 +635,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

 {

-  if(IRQn < 0) {

-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+  if((int32_t)(IRQn) < 0) {

+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

   else {

-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

 }

 

 

@@ -604,10 +660,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

 {

 

-  if(IRQn < 0) {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

+  if((int32_t)(IRQn) < 0) {

+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

   else {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

 }

 

 

@@ -619,10 +677,10 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 {

   __DSB();                                                     /* Ensure all outstanding memory accesses included

                                                                   buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

                  SCB_AIRCR_SYSRESETREQ_Msk);

   __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

+  while(1) { __NOP(); }                                        /* wait until reset */

 }

 

 /*@} end of CMSIS_Core_NVICFunctions */

@@ -655,15 +713,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
  */

 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

 {

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

 

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

                    SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

 }

 

 #endif

@@ -673,10 +731,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 

 

 

-#endif /* __CORE_CM0_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

-

 #ifdef __cplusplus

 }

 #endif

+

+#endif /* __CORE_CM0_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/os/ext/CMSIS/include/core_cm0plus.h b/os/ext/CMSIS/include/core_cm0plus.h
index d1c392314..62e914b50 100644
--- a/os/ext/CMSIS/include/core_cm0plus.h
+++ b/os/ext/CMSIS/include/core_cm0plus.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cm0plus.h

  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2015 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -39,13 +39,13 @@
  #pragma system_include  /* treat file as system include file for MISRA check */

 #endif

 

+#ifndef __CORE_CM0PLUS_H_GENERIC

+#define __CORE_CM0PLUS_H_GENERIC

+

 #ifdef __cplusplus

  extern "C" {

 #endif

 

-#ifndef __CORE_CM0PLUS_H_GENERIC

-#define __CORE_CM0PLUS_H_GENERIC

-

 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

   CMSIS violates the following MISRA-C:2004 rules:

 

@@ -68,8 +68,8 @@
  */

 

 /*  CMSIS CM0P definitions */

-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */

-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */

+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */

 #define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \

                                        __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */

 

@@ -81,14 +81,18 @@
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

   #define __STATIC_INLINE  static __inline

 

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

 #elif defined ( __ICCARM__ )

   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

   #define __STATIC_INLINE  static inline

 

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

   #define __STATIC_INLINE  static inline

 

 #elif defined ( __TASKING__ )

@@ -96,9 +100,16 @@
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

   #define __STATIC_INLINE  static inline

 

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

 #endif

 

-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

 */

 #define __FPU_USED       0

 

@@ -107,13 +118,18 @@
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

 #elif defined ( __ICCARM__ )

   #if defined __ARMVFP__

     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+#elif defined ( __TMS470__ )

+  #if defined __TI__VFP_SUPPORT____

     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

@@ -121,12 +137,21 @@
   #if defined __FPU_VFP__

     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

 #endif

 

 #include <stdint.h>                      /* standard types definitions                      */

 #include <core_cmInstr.h>                /* Core Instruction Access                         */

 #include <core_cmFunc.h>                 /* Core Function Access                            */

 

+#ifdef __cplusplus

+}

+#endif

+

 #endif /* __CORE_CM0PLUS_H_GENERIC */

 

 #ifndef __CMSIS_GENERIC

@@ -134,6 +159,10 @@
 #ifndef __CORE_CM0PLUS_H_DEPENDANT

 #define __CORE_CM0PLUS_H_DEPENDANT

 

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

 /* check device defines and use defaults */

 #if defined __CHECK_DEVICE_DEFINES

   #ifndef __CM0PLUS_REV

@@ -207,14 +236,7 @@ typedef union
 {

   struct

   {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

@@ -223,6 +245,19 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } APSR_Type;

 

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

 

 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).

  */

@@ -236,6 +271,10 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } IPSR_Type;

 

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

  */

@@ -244,16 +283,9 @@ typedef union
   struct

   {

     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

@@ -262,6 +294,25 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } xPSR_Type;

 

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Control Registers (CONTROL).

  */

@@ -271,12 +322,18 @@ typedef union
   {

     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

   } b;                                   /*!< Structure used for bit  access                  */

   uint32_t w;                            /*!< Type      used for word access                  */

 } CONTROL_Type;

 

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

 /*@} end of group CMSIS_CORE */

 

 

@@ -344,7 +401,7 @@ typedef struct
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

 

 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

 

 /* SCB Interrupt Control State Register Definitions */

 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

@@ -372,7 +429,7 @@ typedef struct
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

 

 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

 

 #if (__VTOR_PRESENT == 1)

 /* SCB Interrupt Control State Register Definitions */

@@ -447,15 +504,15 @@ typedef struct
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

 

 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

 

 /* SysTick Reload Register Definitions */

 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

 

 /* SysTick Current Register Definitions */

 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

 

 /* SysTick Calibration Register Definitions */

 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

@@ -465,7 +522,7 @@ typedef struct
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

 

 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

 

 /*@} end of group CMSIS_SysTick */

 

@@ -495,7 +552,7 @@ typedef struct
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

 

 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

 

 /* MPU Control Register */

 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

@@ -505,11 +562,11 @@ typedef struct
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

 

 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

 

 /* MPU Region Number Register */

 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

 

 /* MPU Region Base Address Register */

 #define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */

@@ -519,7 +576,7 @@ typedef struct
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

 

 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

 

 /* MPU Region Attribute and Size Register */

 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

@@ -550,7 +607,7 @@ typedef struct
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

 

 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

 

 /*@} end of group CMSIS_MPU */

 #endif

@@ -612,9 +669,9 @@ typedef struct
 

 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */

 /* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

 

 

 /** \brief  Enable External Interrupt

@@ -625,7 +682,7 @@ typedef struct
  */

 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -637,7 +694,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -653,7 +710,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

 {

-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -665,7 +722,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -677,7 +734,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -692,12 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

 {

-  if(IRQn < 0) {

-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+  if((int32_t)(IRQn) < 0) {

+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

   else {

-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

+  }

 }

 

 

@@ -715,10 +774,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

 {

 

-  if(IRQn < 0) {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

+  if((int32_t)(IRQn) < 0) {

+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

   else {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));

+  }

 }

 

 

@@ -730,10 +791,10 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 {

   __DSB();                                                     /* Ensure all outstanding memory accesses included

                                                                   buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

                  SCB_AIRCR_SYSRESETREQ_Msk);

   __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

+  while(1) { __NOP(); }                                        /* wait until reset */

 }

 

 /*@} end of CMSIS_Core_NVICFunctions */

@@ -766,15 +827,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
  */

 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

 {

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */

 

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

                    SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

 }

 

 #endif

@@ -784,10 +845,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 

 

 

-#endif /* __CORE_CM0PLUS_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

-

 #ifdef __cplusplus

 }

 #endif

+

+#endif /* __CORE_CM0PLUS_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/os/ext/CMSIS/include/core_cm3.h b/os/ext/CMSIS/include/core_cm3.h
index 0e215fc05..d324f9b78 100644
--- a/os/ext/CMSIS/include/core_cm3.h
+++ b/os/ext/CMSIS/include/core_cm3.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cm3.h

  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2015 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -39,13 +39,13 @@
  #pragma system_include  /* treat file as system include file for MISRA check */

 #endif

 

+#ifndef __CORE_CM3_H_GENERIC

+#define __CORE_CM3_H_GENERIC

+

 #ifdef __cplusplus

  extern "C" {

 #endif

 

-#ifndef __CORE_CM3_H_GENERIC

-#define __CORE_CM3_H_GENERIC

-

 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

   CMSIS violates the following MISRA-C:2004 rules:

 

@@ -68,8 +68,8 @@
  */

 

 /*  CMSIS CM3 definitions */

-#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \

                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

 

@@ -81,6 +81,11 @@
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

   #define __STATIC_INLINE  static __inline

 

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

 #elif defined ( __ICCARM__ )

   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

@@ -90,19 +95,21 @@
   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

   #define __STATIC_INLINE  static inline

 

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

 #elif defined ( __TASKING__ )

   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

   #define __STATIC_INLINE  static inline

 

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

 #endif

 

-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

+/** __FPU_USED indicates whether an FPU is used or not.

+    This core does not support an FPU at all

 */

 #define __FPU_USED       0

 

@@ -111,6 +118,11 @@
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

+

 #elif defined ( __ICCARM__ )

   #if defined __ARMVFP__

     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

@@ -121,21 +133,25 @@
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

 

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

 #elif defined ( __TASKING__ )

   #if defined __FPU_VFP__

     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

   #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+  #endif

 #endif

 

 #include <stdint.h>                      /* standard types definitions                      */

 #include <core_cmInstr.h>                /* Core Instruction Access                         */

 #include <core_cmFunc.h>                 /* Core Function Access                            */

 

+#ifdef __cplusplus

+}

+#endif

+

 #endif /* __CORE_CM3_H_GENERIC */

 

 #ifndef __CMSIS_GENERIC

@@ -143,6 +159,10 @@
 #ifndef __CORE_CM3_H_DEPENDANT

 #define __CORE_CM3_H_DEPENDANT

 

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

 /* check device defines and use defaults */

 #if defined __CHECK_DEVICE_DEFINES

   #ifndef __CM3_REV

@@ -212,13 +232,7 @@ typedef union
 {

   struct

   {

-#if (__CORTEX_M != 0x04)

     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

@@ -228,6 +242,22 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } APSR_Type;

 

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */

+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

+

 

 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).

  */

@@ -241,6 +271,10 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } IPSR_Type;

 

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

  */

@@ -249,13 +283,7 @@ typedef union
   struct

   {

     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

@@ -267,6 +295,31 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } xPSR_Type;

 

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */

+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

+

+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */

+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Control Registers (CONTROL).

  */

@@ -276,12 +329,18 @@ typedef union
   {

     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */

   } b;                                   /*!< Structure used for bit  access                  */

   uint32_t w;                            /*!< Type      used for word access                  */

 } CONTROL_Type;

 

+/* CONTROL Register Definitions */

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

 /*@} end of group CMSIS_CORE */

 

 

@@ -312,7 +371,7 @@ typedef struct
 

 /* Software Triggered Interrupt Register Definitions */

 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

 

 /*@} end of group CMSIS_NVIC */

 

@@ -364,7 +423,7 @@ typedef struct
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

 

 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

 

 /* SCB Interrupt Control State Register Definitions */

 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

@@ -395,7 +454,7 @@ typedef struct
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

 

 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

 

 /* SCB Vector Table Offset Register Definitions */

 #if (__CM3_REV < 0x0201)                   /* core r2p1 */

@@ -429,7 +488,7 @@ typedef struct
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

 

 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

 

 /* SCB System Control Register Definitions */

 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

@@ -458,7 +517,7 @@ typedef struct
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

 

 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

 

 /* SCB System Handler Control and State Register Definitions */

 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

@@ -501,7 +560,7 @@ typedef struct
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

 

 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

 

 /* SCB Configurable Fault Status Registers Definitions */

 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

@@ -511,7 +570,7 @@ typedef struct
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

 

 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

 

 /* SCB Hard Fault Status Registers Definitions */

 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

@@ -537,7 +596,7 @@ typedef struct
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

 

 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

 

 /*@} end of group CMSIS_SCB */

 

@@ -563,7 +622,7 @@ typedef struct
 

 /* Interrupt Controller Type Register Definitions */

 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

 

 /* Auxiliary Control Register Definitions */

 

@@ -574,7 +633,7 @@ typedef struct
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

 

 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

 

 /*@} end of group CMSIS_SCnotSCB */

 

@@ -606,15 +665,15 @@ typedef struct
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

 

 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

 

 /* SysTick Reload Register Definitions */

 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

 

 /* SysTick Current Register Definitions */

 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

 

 /* SysTick Calibration Register Definitions */

 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

@@ -624,7 +683,7 @@ typedef struct
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

 

 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

 

 /*@} end of group CMSIS_SysTick */

 

@@ -675,7 +734,7 @@ typedef struct
 

 /* ITM Trace Privilege Register Definitions */

 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

 

 /* ITM Trace Control Register Definitions */

 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

@@ -703,19 +762,19 @@ typedef struct
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

 

 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

 

 /* ITM Integration Write Register Definitions */

 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

 

 /* ITM Integration Read Register Definitions */

 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

 

 /* ITM Integration Mode Control Register Definitions */

 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

 

 /* ITM Lock Status Register Definitions */

 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

@@ -725,7 +784,7 @@ typedef struct
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

 

 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

 

 /*@}*/ /* end of group CMSIS_ITM */

 

@@ -818,31 +877,31 @@ typedef struct
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

 

 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

 

 /* DWT CPI Count Register Definitions */

 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

 

 /* DWT Exception Overhead Count Register Definitions */

 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

 

 /* DWT Sleep Count Register Definitions */

 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

 

 /* DWT LSU Count Register Definitions */

 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

 

 /* DWT Folded-instruction Count Register Definitions */

 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

 

 /* DWT Comparator Mask Register Definitions */

 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

 

 /* DWT Comparator Function Register Definitions */

 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

@@ -870,7 +929,7 @@ typedef struct
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

 

 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

 

 /*@}*/ /* end of group CMSIS_DWT */

 

@@ -913,11 +972,11 @@ typedef struct
 

 /* TPI Asynchronous Clock Prescaler Register Definitions */

 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

 

 /* TPI Selected Pin Protocol Register Definitions */

 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

 

 /* TPI Formatter and Flush Status Register Definitions */

 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

@@ -930,7 +989,7 @@ typedef struct
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

 

 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

 

 /* TPI Formatter and Flush Control Register Definitions */

 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

@@ -941,7 +1000,7 @@ typedef struct
 

 /* TPI TRIGGER Register Definitions */

 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

 

 /* TPI Integration ETM Data Register Definitions (FIFO0) */

 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

@@ -963,11 +1022,11 @@ typedef struct
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

 

 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

 

 /* TPI ITATBCTR2 Register Definitions */

 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

 

 /* TPI Integration ITM Data Register Definitions (FIFO1) */

 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

@@ -989,15 +1048,15 @@ typedef struct
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

 

 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

 

 /* TPI ITATBCTR0 Register Definitions */

 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

 

 /* TPI Integration Mode Control Register Definitions */

 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

 

 /* TPI DEVID Register Definitions */

 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

@@ -1016,15 +1075,15 @@ typedef struct
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

 

 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

 

 /* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

 

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

+

 /*@}*/ /* end of group CMSIS_TPI */

 

 

@@ -1060,7 +1119,7 @@ typedef struct
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

 

 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

 

 /* MPU Control Register */

 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

@@ -1070,11 +1129,11 @@ typedef struct
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

 

 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

 

 /* MPU Region Number Register */

 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

 

 /* MPU Region Base Address Register */

 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

@@ -1084,7 +1143,7 @@ typedef struct
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

 

 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

 

 /* MPU Region Attribute and Size Register */

 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

@@ -1115,7 +1174,7 @@ typedef struct
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

 

 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

 

 /*@} end of group CMSIS_MPU */

 #endif

@@ -1172,14 +1231,14 @@ typedef struct
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

 

 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

 

 /* Debug Core Register Selector Register */

 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

 

 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

 

 /* Debug Exception and Monitor Control Register */

 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

@@ -1219,7 +1278,7 @@ typedef struct
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

 

 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

 

 /*@} end of group CMSIS_CoreDebug */

 

@@ -1291,13 +1350,13 @@ typedef struct
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

 {

   uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

 

   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */

+  reg_value  =  (reg_value                                   |

+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */

   SCB->AIRCR =  reg_value;

 }

 

@@ -1310,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  */

 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

 {

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

 }

 

 

@@ -1322,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  */

 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */

+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1334,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1350,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

 {

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -1362,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1374,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1389,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

 {

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -1404,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

 {

-  if(IRQn < 0) {

-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

+  if((int32_t)IRQn < 0) {

+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

   else {

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

 }

 

 

@@ -1425,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

 {

 

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

+  if((int32_t)IRQn < 0) {

+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));

+  }

   else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));

+  }

 }

 

 

@@ -1437,7 +1500,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
     The function encodes the priority for an interrupt with the given priority group,

     preemptive priority value, and subpriority value.

     In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

 

     \param [in]     PriorityGroup  Used priority group.

     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

@@ -1446,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

 {

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

   uint32_t PreemptPriorityBits;

   uint32_t SubPriorityBits;

 

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

 

   return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

          );

 }

 

@@ -1465,7 +1528,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
     The function decodes an interrupt priority value with a given priority group to

     preemptive priority value and subpriority value.

     In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

 

     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

     \param [in]     PriorityGroup  Used priority group.

@@ -1474,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
  */

 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

 {

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

   uint32_t PreemptPriorityBits;

   uint32_t SubPriorityBits;

 

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

 

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

 }

 

 

@@ -1492,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
  */

 __STATIC_INLINE void NVIC_SystemReset(void)

 {

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

+  __DSB();                                                          /* Ensure all outstanding memory accesses included

+                                                                       buffered write are completed before reset */

+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

+  __DSB();                                                          /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                             /* wait until reset */

 }

 

 /*@} end of CMSIS_Core_NVICFunctions */

@@ -1531,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
  */

 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

 {

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

 

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

                    SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

 }

 

 #endif

@@ -1571,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
  */

 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

 {

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

   {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }

+    ITM->PORT[0].u8 = (uint8_t)ch;

   }

   return (ch);

 }

@@ -1618,10 +1681,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
 

 /*@} end of CMSIS_core_DebugFunctions */

 

-#endif /* __CORE_CM3_H_DEPENDANT */

 

-#endif /* __CMSIS_GENERIC */

+

 

 #ifdef __cplusplus

 }

 #endif

+

+#endif /* __CORE_CM3_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/os/ext/CMSIS/include/core_cm4.h b/os/ext/CMSIS/include/core_cm4.h
index 2c8b0882c..544d41484 100644
--- a/os/ext/CMSIS/include/core_cm4.h
+++ b/os/ext/CMSIS/include/core_cm4.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cm4.h

  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2015 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -39,13 +39,13 @@
  #pragma system_include  /* treat file as system include file for MISRA check */

 #endif

 

+#ifndef __CORE_CM4_H_GENERIC

+#define __CORE_CM4_H_GENERIC

+

 #ifdef __cplusplus

  extern "C" {

 #endif

 

-#ifndef __CORE_CM4_H_GENERIC

-#define __CORE_CM4_H_GENERIC

-

 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

   CMSIS violates the following MISRA-C:2004 rules:

 

@@ -68,8 +68,8 @@
  */

 

 /*  CMSIS CM4 definitions */

-#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \

                                     __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

 

@@ -81,6 +81,11 @@
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

   #define __STATIC_INLINE  static __inline

 

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

 #elif defined ( __ICCARM__ )

   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

@@ -90,19 +95,21 @@
   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

   #define __STATIC_INLINE  static inline

 

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

 #elif defined ( __TASKING__ )

   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

   #define __STATIC_INLINE  static inline

 

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

 #endif

 

-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+/** __FPU_USED indicates whether an FPU is used or not.

+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

 */

 #if defined ( __CC_ARM )

   #if defined __TARGET_FPU_VFP

@@ -116,6 +123,18 @@
     #define __FPU_USED         0

   #endif

 

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

 #elif defined ( __ICCARM__ )

   #if defined __ARMVFP__

     #if (__FPU_PRESENT == 1)

@@ -140,20 +159,20 @@
     #define __FPU_USED         0

   #endif

 

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

     #if (__FPU_PRESENT == 1)

       #define __FPU_USED       1

     #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

       #define __FPU_USED       0

     #endif

   #else

     #define __FPU_USED         0

   #endif

 

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

     #if (__FPU_PRESENT == 1)

       #define __FPU_USED       1

     #else

@@ -168,7 +187,11 @@
 #include <stdint.h>                      /* standard types definitions                      */

 #include <core_cmInstr.h>                /* Core Instruction Access                         */

 #include <core_cmFunc.h>                 /* Core Function Access                            */

-#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */

+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

+

+#ifdef __cplusplus

+}

+#endif

 

 #endif /* __CORE_CM4_H_GENERIC */

 

@@ -177,6 +200,10 @@
 #ifndef __CORE_CM4_H_DEPENDANT

 #define __CORE_CM4_H_DEPENDANT

 

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

 /* check device defines and use defaults */

 #if defined __CHECK_DEVICE_DEFINES

   #ifndef __CM4_REV

@@ -252,13 +279,9 @@ typedef union
 {

   struct

   {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

@@ -268,6 +291,25 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } APSR_Type;

 

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */

+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

+

+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */

+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */

+

 

 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).

  */

@@ -281,6 +323,10 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } IPSR_Type;

 

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

  */

@@ -289,13 +335,9 @@ typedef union
   struct

   {

     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

@@ -307,6 +349,34 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } xPSR_Type;

 

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */

+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

+

+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */

+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */

+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

 

 /** \brief  Union type to access the Control Registers (CONTROL).

  */

@@ -322,6 +392,16 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */

 } CONTROL_Type;

 

+/* CONTROL Register Definitions */

+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */

+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */

+

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

 /*@} end of group CMSIS_CORE */

 

 

@@ -352,7 +432,7 @@ typedef struct
 

 /* Software Triggered Interrupt Register Definitions */

 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

 

 /*@} end of group CMSIS_NVIC */

 

@@ -404,7 +484,7 @@ typedef struct
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

 

 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

 

 /* SCB Interrupt Control State Register Definitions */

 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

@@ -435,7 +515,7 @@ typedef struct
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

 

 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

 

 /* SCB Vector Table Offset Register Definitions */

 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

@@ -461,7 +541,7 @@ typedef struct
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

 

 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

 

 /* SCB System Control Register Definitions */

 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

@@ -490,7 +570,7 @@ typedef struct
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

 

 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

 

 /* SCB System Handler Control and State Register Definitions */

 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

@@ -533,7 +613,7 @@ typedef struct
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

 

 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

 

 /* SCB Configurable Fault Status Registers Definitions */

 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

@@ -543,7 +623,7 @@ typedef struct
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

 

 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

 

 /* SCB Hard Fault Status Registers Definitions */

 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

@@ -569,7 +649,7 @@ typedef struct
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

 

 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

 

 /*@} end of group CMSIS_SCB */

 

@@ -591,7 +671,7 @@ typedef struct
 

 /* Interrupt Controller Type Register Definitions */

 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

 

 /* Auxiliary Control Register Definitions */

 #define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */

@@ -607,7 +687,7 @@ typedef struct
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

 

 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

 

 /*@} end of group CMSIS_SCnotSCB */

 

@@ -639,15 +719,15 @@ typedef struct
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

 

 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

 

 /* SysTick Reload Register Definitions */

 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

 

 /* SysTick Current Register Definitions */

 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

 

 /* SysTick Calibration Register Definitions */

 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

@@ -657,7 +737,7 @@ typedef struct
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

 

 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

 

 /*@} end of group CMSIS_SysTick */

 

@@ -708,7 +788,7 @@ typedef struct
 

 /* ITM Trace Privilege Register Definitions */

 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

 

 /* ITM Trace Control Register Definitions */

 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

@@ -736,19 +816,19 @@ typedef struct
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

 

 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

 

 /* ITM Integration Write Register Definitions */

 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

 

 /* ITM Integration Read Register Definitions */

 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

 

 /* ITM Integration Mode Control Register Definitions */

 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

 

 /* ITM Lock Status Register Definitions */

 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

@@ -758,7 +838,7 @@ typedef struct
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

 

 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

 

 /*@}*/ /* end of group CMSIS_ITM */

 

@@ -851,31 +931,31 @@ typedef struct
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

 

 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

 

 /* DWT CPI Count Register Definitions */

 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

 

 /* DWT Exception Overhead Count Register Definitions */

 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

 

 /* DWT Sleep Count Register Definitions */

 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

 

 /* DWT LSU Count Register Definitions */

 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

 

 /* DWT Folded-instruction Count Register Definitions */

 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

 

 /* DWT Comparator Mask Register Definitions */

 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

 

 /* DWT Comparator Function Register Definitions */

 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

@@ -903,7 +983,7 @@ typedef struct
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

 

 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

 

 /*@}*/ /* end of group CMSIS_DWT */

 

@@ -946,11 +1026,11 @@ typedef struct
 

 /* TPI Asynchronous Clock Prescaler Register Definitions */

 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

 

 /* TPI Selected Pin Protocol Register Definitions */

 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

 

 /* TPI Formatter and Flush Status Register Definitions */

 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

@@ -963,7 +1043,7 @@ typedef struct
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

 

 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

 

 /* TPI Formatter and Flush Control Register Definitions */

 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

@@ -974,7 +1054,7 @@ typedef struct
 

 /* TPI TRIGGER Register Definitions */

 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

 

 /* TPI Integration ETM Data Register Definitions (FIFO0) */

 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

@@ -996,11 +1076,11 @@ typedef struct
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

 

 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

 

 /* TPI ITATBCTR2 Register Definitions */

 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

 

 /* TPI Integration ITM Data Register Definitions (FIFO1) */

 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

@@ -1022,15 +1102,15 @@ typedef struct
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

 

 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

 

 /* TPI ITATBCTR0 Register Definitions */

 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

 

 /* TPI Integration Mode Control Register Definitions */

 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

 

 /* TPI DEVID Register Definitions */

 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

@@ -1049,15 +1129,15 @@ typedef struct
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

 

 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

 

 /* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

 

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

+

 /*@}*/ /* end of group CMSIS_TPI */

 

 

@@ -1093,7 +1173,7 @@ typedef struct
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

 

 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

 

 /* MPU Control Register */

 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

@@ -1103,11 +1183,11 @@ typedef struct
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

 

 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

 

 /* MPU Region Number Register */

 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

 

 /* MPU Region Base Address Register */

 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

@@ -1117,7 +1197,7 @@ typedef struct
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

 

 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

 

 /* MPU Region Attribute and Size Register */

 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

@@ -1148,7 +1228,7 @@ typedef struct
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

 

 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

 

 /*@} end of group CMSIS_MPU */

 #endif

@@ -1199,7 +1279,7 @@ typedef struct
 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

 

 #define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */

+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */

 

 /* Floating-Point Context Address Register */

 #define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

@@ -1241,7 +1321,7 @@ typedef struct
 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

 

 #define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */

+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

 

 /* Media and FP Feature Register 1 */

 #define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

@@ -1254,7 +1334,7 @@ typedef struct
 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

 

 #define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */

+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

 

 /*@} end of group CMSIS_FPU */

 #endif

@@ -1311,14 +1391,14 @@ typedef struct
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

 

 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

 

 /* Debug Core Register Selector Register */

 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

 

 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

 

 /* Debug Exception and Monitor Control Register */

 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

@@ -1358,7 +1438,7 @@ typedef struct
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

 

 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

 

 /*@} end of group CMSIS_CoreDebug */

 

@@ -1435,13 +1515,13 @@ typedef struct
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

 {

   uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

 

   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */

+  reg_value  =  (reg_value                                   |

+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */

   SCB->AIRCR =  reg_value;

 }

 

@@ -1454,7 +1534,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  */

 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

 {

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

 }

 

 

@@ -1466,8 +1546,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  */

 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

 {

-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */

-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */

+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1479,7 +1558,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1495,7 +1574,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

 {

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -1507,7 +1586,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1519,7 +1598,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

 {

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

 }

 

 

@@ -1534,7 +1613,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

 {

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

 }

 

 

@@ -1549,10 +1628,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */

 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

 {

-  if(IRQn < 0) {

-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

+  if((int32_t)IRQn < 0) {

+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

   else {

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

 }

 

 

@@ -1570,10 +1651,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

 {

 

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

+  if((int32_t)IRQn < 0) {

+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));

+  }

   else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));

+  }

 }

 

 

@@ -1582,7 +1665,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
     The function encodes the priority for an interrupt with the given priority group,

     preemptive priority value, and subpriority value.

     In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

 

     \param [in]     PriorityGroup  Used priority group.

     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

@@ -1591,16 +1674,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  */

 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

 {

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

   uint32_t PreemptPriorityBits;

   uint32_t SubPriorityBits;

 

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

 

   return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

          );

 }

 

@@ -1610,7 +1693,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
     The function decodes an interrupt priority value with a given priority group to

     preemptive priority value and subpriority value.

     In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

 

     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

     \param [in]     PriorityGroup  Used priority group.

@@ -1619,15 +1702,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
  */

 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

 {

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

   uint32_t PreemptPriorityBits;

   uint32_t SubPriorityBits;

 

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

 

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

 }

 

 

@@ -1637,13 +1720,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
  */

 __STATIC_INLINE void NVIC_SystemReset(void)

 {

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

+  __DSB();                                                          /* Ensure all outstanding memory accesses included

+                                                                       buffered write are completed before reset */

+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

+  __DSB();                                                          /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                             /* wait until reset */

 }

 

 /*@} end of CMSIS_Core_NVICFunctions */

@@ -1676,15 +1759,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
  */

 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

 {

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

 

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

                    SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

 }

 

 #endif

@@ -1716,11 +1799,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
  */

 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

 {

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

   {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }

+    ITM->PORT[0].u8 = (uint8_t)ch;

   }

   return (ch);

 }

@@ -1763,10 +1846,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
 

 /*@} end of CMSIS_core_DebugFunctions */

 

-#endif /* __CORE_CM4_H_DEPENDANT */

 

-#endif /* __CMSIS_GENERIC */

+

 

 #ifdef __cplusplus

 }

 #endif

+

+#endif /* __CORE_CM4_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/os/ext/CMSIS/include/core_cm7.h b/os/ext/CMSIS/include/core_cm7.h
new file mode 100644
index 000000000..cb19b9fac
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm7.h
@@ -0,0 +1,2397 @@
+/**************************************************************************//**

+ * @file     core_cm7.h

+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File

+ * @version  V4.10

+ * @date     18. March 2015

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2015 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM7_H_GENERIC

+#define __CORE_CM7_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_M7

+  @{

+ */

+

+/*  CMSIS CM7 definitions */

+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \

+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+*/

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI_VFP_SUPPORT__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM7_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM7_H_DEPENDANT

+#define __CORE_CM7_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM7_REV

+    #define __CM7_REV               0x0000

+    #warning "__CM7_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __FPU_PRESENT

+    #define __FPU_PRESENT             0

+    #warning "__FPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __MPU_PRESENT

+    #define __MPU_PRESENT             0

+    #warning "__MPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __ICACHE_PRESENT

+    #define __ICACHE_PRESENT          0

+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __DCACHE_PRESENT

+    #define __DCACHE_PRESENT          0

+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __DTCM_PRESENT

+    #define __DTCM_PRESENT            0

+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          3

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_M7 */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+  - Core Debug Register

+  - Core MPU Register

+  - Core FPU Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+/* APSR Register Definitions */

+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */

+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

+

+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */

+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

+

+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */

+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

+

+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */

+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

+

+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */

+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

+

+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */

+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+/* IPSR Register Definitions */

+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */

+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+/* xPSR Register Definitions */

+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */

+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

+

+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */

+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

+

+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */

+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

+

+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */

+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

+

+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */

+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

+

+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */

+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

+

+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */

+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

+

+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */

+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */

+

+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */

+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/* CONTROL Register Definitions */

+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */

+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */

+

+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */

+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

+

+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */

+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[24];

+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

+       uint32_t RSERVED1[24];

+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

+       uint32_t RESERVED2[24];

+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

+       uint32_t RESERVED3[24];

+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

+       uint32_t RESERVED4[56];

+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

+       uint32_t RESERVED5[644];

+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

+}  NVIC_Type;

+

+/* Software Triggered Interrupt Register Definitions */

+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

+       uint32_t RESERVED0[1];

+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */

+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */

+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */

+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */

+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

+       uint32_t RESERVED3[93];

+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */

+       uint32_t RESERVED4[15];

+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */

+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */

+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */

+       uint32_t RESERVED5[1];

+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */

+       uint32_t RESERVED6[1];

+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */

+  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */

+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */

+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */

+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */

+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */

+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */

+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */

+       uint32_t RESERVED7[6];

+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */

+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */

+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */

+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */

+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */

+       uint32_t RESERVED8[1];

+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Vector Table Offset Register Definitions */

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */

+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */

+

+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */

+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */

+

+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */

+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */

+

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

+

+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

+

+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

+

+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

+

+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

+

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

+

+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

+

+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

+

+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

+

+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

+

+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

+

+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

+

+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

+

+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

+

+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

+

+/* SCB Configurable Fault Status Registers Definitions */

+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

+

+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

+

+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+

+/* SCB Hard Fault Status Registers Definitions */

+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

+

+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

+

+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

+

+/* SCB Debug Fault Status Register Definitions */

+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

+

+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

+

+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

+

+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

+

+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

+

+/* Cache Level ID register */

+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */

+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */

+

+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */

+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */

+

+/* Cache Type register */

+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */

+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */

+

+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */

+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */

+

+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */

+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */

+

+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */

+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */

+

+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */

+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */

+

+/* Cache Size ID Register */

+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */

+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */

+

+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */

+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */

+

+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */

+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */

+

+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */

+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */

+

+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */

+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */

+

+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */

+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */

+

+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */

+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */

+

+/* Cache Size Selection Register */

+#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */

+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */

+

+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */

+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */

+

+/* SCB Software Triggered Interrupt Register */

+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */

+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */

+

+/* Instruction Tightly-Coupled Memory Control Register*/

+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */

+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */

+

+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */

+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */

+

+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */

+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */

+

+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */

+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */

+

+/* Data Tightly-Coupled Memory Control Registers */

+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */

+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */

+

+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */

+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */

+

+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */

+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */

+

+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */

+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */

+

+/* AHBP Control Register */

+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */

+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */

+

+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */

+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */

+

+/* L1 Cache Control Register */

+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */

+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */

+

+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */

+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */

+

+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */

+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */

+

+/* AHBS control register */

+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */

+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */

+

+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */

+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */

+

+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/

+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */

+

+/* Auxiliary Bus Fault Status Register */

+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/

+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */

+

+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/

+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */

+

+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/

+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */

+

+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/

+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */

+

+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/

+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */

+

+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/

+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

+    \brief      Type definitions for the System Control and ID Register not in the SCB

+  @{

+ */

+

+/** \brief  Structure type to access the System Control and ID Register not in the SCB.

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */

+} SCnSCB_Type;

+

+/* Interrupt Controller Type Register Definitions */

+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

+

+/* Auxiliary Control Register Definitions */

+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */

+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */

+

+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */

+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */

+

+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */

+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */

+

+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

+

+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

+

+/*@} end of group CMSIS_SCnotSCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

+  @{

+ */

+

+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

+ */

+typedef struct

+{

+  __O  union

+  {

+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

+       uint32_t RESERVED0[864];

+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

+       uint32_t RESERVED1[15];

+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

+       uint32_t RESERVED2[15];

+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

+       uint32_t RESERVED3[29];

+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

+       uint32_t RESERVED4[43];

+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

+       uint32_t RESERVED5[6];

+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

+} ITM_Type;

+

+/* ITM Trace Privilege Register Definitions */

+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

+

+/* ITM Trace Control Register Definitions */

+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

+

+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

+

+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

+

+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

+

+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

+

+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

+

+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

+

+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

+

+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

+

+/* ITM Integration Write Register Definitions */

+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

+

+/* ITM Integration Read Register Definitions */

+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

+

+/* ITM Integration Mode Control Register Definitions */

+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

+

+/* ITM Lock Status Register Definitions */

+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

+

+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

+

+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

+

+/*@}*/ /* end of group CMSIS_ITM */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

+  @{

+ */

+

+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

+       uint32_t RESERVED0[1];

+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

+       uint32_t RESERVED1[1];

+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

+       uint32_t RESERVED2[1];

+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

+       uint32_t RESERVED3[981];

+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */

+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */

+} DWT_Type;

+

+/* DWT Control Register Definitions */

+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

+

+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

+

+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

+

+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

+

+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

+

+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

+

+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

+

+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

+

+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

+

+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

+

+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

+

+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

+

+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

+

+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

+

+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

+

+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

+

+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

+

+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

+

+/* DWT CPI Count Register Definitions */

+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

+

+/* DWT Exception Overhead Count Register Definitions */

+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

+

+/* DWT Sleep Count Register Definitions */

+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+

+/* DWT LSU Count Register Definitions */

+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

+

+/* DWT Folded-instruction Count Register Definitions */

+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

+

+/* DWT Comparator Mask Register Definitions */

+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

+

+/* DWT Comparator Function Register Definitions */

+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

+

+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

+

+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

+

+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

+

+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

+

+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

+

+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

+

+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

+

+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

+

+/*@}*/ /* end of group CMSIS_DWT */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

+    \brief      Type definitions for the Trace Port Interface (TPI)

+  @{

+ */

+

+/** \brief  Structure type to access the Trace Port Interface Register (TPI).

+ */

+typedef struct

+{

+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

+       uint32_t RESERVED0[2];

+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

+       uint32_t RESERVED1[55];

+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

+       uint32_t RESERVED2[131];

+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

+       uint32_t RESERVED3[759];

+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

+       uint32_t RESERVED4[1];

+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

+       uint32_t RESERVED5[39];

+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

+       uint32_t RESERVED7[8];

+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

+} TPI_Type;

+

+/* TPI Asynchronous Clock Prescaler Register Definitions */

+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

+

+/* TPI Selected Pin Protocol Register Definitions */

+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

+

+/* TPI Formatter and Flush Status Register Definitions */

+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

+

+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

+

+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

+

+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

+

+/* TPI Formatter and Flush Control Register Definitions */

+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

+

+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

+

+/* TPI TRIGGER Register Definitions */

+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

+

+/* TPI Integration ETM Data Register Definitions (FIFO0) */

+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

+

+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

+

+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

+

+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

+

+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

+

+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

+

+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

+

+/* TPI ITATBCTR2 Register Definitions */

+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

+

+/* TPI Integration ITM Data Register Definitions (FIFO1) */

+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

+

+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

+

+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

+

+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

+

+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

+

+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

+

+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

+

+/* TPI ITATBCTR0 Register Definitions */

+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

+

+/* TPI Integration Mode Control Register Definitions */

+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

+

+/* TPI DEVID Register Definitions */

+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

+

+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

+

+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

+

+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

+

+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

+

+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

+

+/* TPI DEVTYPE Register Definitions */

+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

+

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

+

+/*@}*/ /* end of group CMSIS_TPI */

+

+

+#if (__MPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

+    \brief      Type definitions for the Memory Protection Unit (MPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Memory Protection Unit (MPU).

+ */

+typedef struct

+{

+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

+} MPU_Type;

+

+/* MPU Type Register */

+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

+

+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

+

+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

+

+/* MPU Control Register */

+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

+

+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

+

+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

+

+/* MPU Region Number Register */

+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

+

+/* MPU Region Base Address Register */

+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

+

+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

+

+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

+

+/* MPU Region Attribute and Size Register */

+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

+

+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

+

+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

+

+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

+

+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

+

+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

+

+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

+

+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

+

+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

+

+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

+

+/*@} end of group CMSIS_MPU */

+#endif

+

+

+#if (__FPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)

+    \brief      Type definitions for the Floating Point Unit (FPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Floating Point Unit (FPU).

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */

+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */

+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */

+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */

+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */

+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */

+} FPU_Type;

+

+/* Floating-Point Context Control Register */

+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */

+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

+

+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */

+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

+

+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */

+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

+

+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */

+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

+

+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */

+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

+

+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */

+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

+

+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */

+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

+

+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */

+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

+

+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */

+

+/* Floating-Point Context Address Register */

+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

+

+/* Floating-Point Default Status Control Register */

+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */

+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

+

+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */

+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

+

+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */

+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

+

+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */

+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

+

+/* Media and FP Feature Register 0 */

+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */

+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

+

+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */

+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

+

+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */

+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

+

+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */

+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

+

+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */

+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

+

+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */

+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

+

+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */

+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

+

+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

+

+/* Media and FP Feature Register 1 */

+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

+

+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */

+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

+

+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */

+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

+

+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

+

+/* Media and FP Feature Register 2 */

+

+/*@} end of group CMSIS_FPU */

+#endif

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Type definitions for the Core Debug Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Core Debug Register (CoreDebug).

+ */

+typedef struct

+{

+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

+} CoreDebug_Type;

+

+/* Debug Halting Control and Status Register */

+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

+

+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

+

+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

+

+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

+

+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

+

+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

+

+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

+

+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

+

+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

+

+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

+

+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

+

+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+

+/* Debug Core Register Selector Register */

+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

+

+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

+

+/* Debug Exception and Monitor Control Register */

+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

+

+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

+

+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

+

+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

+

+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

+

+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

+

+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

+

+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

+

+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

+

+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

+

+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

+

+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

+

+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M4 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

+

+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

+

+#if (__MPU_PRESENT == 1)

+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

+#endif

+

+#if (__FPU_PRESENT == 1)

+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */

+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */

+#endif

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Debug Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/** \brief  Set Priority Grouping

+

+  The function sets the priority grouping field using the required unlock sequence.

+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

+  Only values from 0..7 are used.

+  In case of a conflict between priority grouping and available

+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]      PriorityGroup  Priority grouping field.

+ */

+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

+{

+  uint32_t reg_value;

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

+

+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */

+  reg_value  =  (reg_value                                   |

+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */

+  SCB->AIRCR =  reg_value;

+}

+

+

+/** \brief  Get Priority Grouping

+

+  The function reads the priority grouping field from the NVIC Interrupt Controller.

+

+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

+{

+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

+}

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

+}

+

+

+/** \brief  Get Active Interrupt

+

+    The function reads the active register in NVIC and returns the active bit.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not active.

+    \return             1  Interrupt status is active.

+ */

+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

+{

+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if((int32_t)IRQn < 0) {

+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+  else {

+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

+  }

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if((int32_t)IRQn < 0) {

+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));

+  }

+  else {

+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));

+  }

+}

+

+

+/** \brief  Encode Priority

+

+    The function encodes the priority for an interrupt with the given priority group,

+    preemptive priority value, and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]     PriorityGroup  Used priority group.

+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

+    \param [in]       SubPriority  Subpriority value (starting from 0).

+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

+ */

+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  return (

+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

+         );

+}

+

+

+/** \brief  Decode Priority

+

+    The function decodes an interrupt priority value with a given priority group to

+    preemptive priority value and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+

+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

+    \param [in]     PriorityGroup  Used priority group.

+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

+    \param [out]     pSubPriority  Subpriority value (starting from 0).

+ */

+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

+

+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+{

+  __DSB();                                                          /* Ensure all outstanding memory accesses included

+                                                                       buffered write are completed before reset */

+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

+  __DSB();                                                          /* Ensure completion of memory access */

+  while(1) { __NOP(); }                                             /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+/* ##########################  FPU functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_FpuFunctions FPU Functions

+    \brief      Function that provides FPU type.

+    @{

+ */

+

+/**

+  \fn          uint32_t SCB_GetFPUType(void)

+  \brief       get FPU type

+  \returns

+   - \b  0: No FPU

+   - \b  1: Single precision FPU

+   - \b  2: Double + Single precision FPU

+ */

+__STATIC_INLINE uint32_t SCB_GetFPUType(void)

+{

+  uint32_t mvfr0;

+

+  mvfr0 = SCB->MVFR0;

+  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {

+    return 2UL;           // Double + Single precision FPU

+  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {

+    return 1UL;           // Single precision FPU

+  } else {

+    return 0UL;           // No FPU

+  }

+}

+

+

+/*@} end of CMSIS_Core_FpuFunctions */

+

+

+

+/* ##########################  Cache functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_CacheFunctions Cache Functions

+    \brief      Functions that configure Instruction and Data cache.

+    @{

+ */

+

+/* Cache Size ID Register Macros */

+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )

+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )

+

+

+/** \brief Enable I-Cache

+

+    The function turns on I-Cache

+  */

+__STATIC_INLINE void SCB_EnableICache (void)

+{

+  #if (__ICACHE_PRESENT == 1)

+    __DSB();

+    __ISB();

+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache

+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Disable I-Cache

+

+    The function turns off I-Cache

+  */

+__STATIC_INLINE void SCB_DisableICache (void)

+{

+  #if (__ICACHE_PRESENT == 1)

+    __DSB();

+    __ISB();

+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache

+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Invalidate I-Cache

+

+    The function invalidates I-Cache

+  */

+__STATIC_INLINE void SCB_InvalidateICache (void)

+{

+  #if (__ICACHE_PRESENT == 1)

+    __DSB();

+    __ISB();

+    SCB->ICIALLU = 0UL;

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Enable D-Cache

+

+    The function turns on D-Cache

+  */

+__STATIC_INLINE void SCB_EnableDCache (void)

+{

+  #if (__DCACHE_PRESENT == 1)

+    uint32_t ccsidr, sshift, wshift, sw;

+    uint32_t sets, ways;

+

+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache

+    ccsidr  = SCB->CCSIDR;

+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));

+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);

+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));

+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);

+

+    __DSB();

+

+    do {                                   // invalidate D-Cache

+         uint32_t tmpways = ways;

+         do {

+              sw = ((tmpways << wshift) | (sets << sshift));

+              SCB->DCISW = sw;

+            } while(tmpways--);

+        } while(sets--);

+    __DSB();

+

+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Disable D-Cache

+

+    The function turns off D-Cache

+  */

+__STATIC_INLINE void SCB_DisableDCache (void)

+{

+  #if (__DCACHE_PRESENT == 1)

+    uint32_t ccsidr, sshift, wshift, sw;

+    uint32_t sets, ways;

+

+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache

+    ccsidr  = SCB->CCSIDR;

+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));

+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);

+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));

+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);

+

+    __DSB();

+

+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache

+

+    do {                                    // clean & invalidate D-Cache

+         uint32_t tmpways = ways;

+         do {

+              sw = ((tmpways << wshift) | (sets << sshift));

+              SCB->DCCISW = sw;

+            } while(tmpways--);

+        } while(sets--);

+

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Invalidate D-Cache

+

+    The function invalidates D-Cache

+  */

+__STATIC_INLINE void SCB_InvalidateDCache (void)

+{

+  #if (__DCACHE_PRESENT == 1)

+    uint32_t ccsidr, sshift, wshift, sw;

+    uint32_t sets, ways;

+

+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache

+    ccsidr  = SCB->CCSIDR;

+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));

+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);

+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));

+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);

+

+    __DSB();

+

+    do {                                    // invalidate D-Cache

+         uint32_t tmpways = ways;

+         do {

+              sw = ((tmpways << wshift) | (sets << sshift));

+              SCB->DCISW = sw;

+            } while(tmpways--);

+        } while(sets--);

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Clean D-Cache

+

+    The function cleans D-Cache

+  */

+__STATIC_INLINE void SCB_CleanDCache (void)

+{

+  #if (__DCACHE_PRESENT == 1)

+    uint32_t ccsidr, sshift, wshift, sw;

+    uint32_t sets, ways;

+

+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache

+    ccsidr  = SCB->CCSIDR;

+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));

+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);

+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));

+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);

+

+    __DSB();

+

+    do {                                    // clean D-Cache

+         uint32_t tmpways = ways;

+         do {

+              sw = ((tmpways << wshift) | (sets << sshift));

+              SCB->DCCSW = sw;

+            } while(tmpways--);

+        } while(sets--);

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/** \brief Clean & Invalidate D-Cache

+

+    The function cleans and Invalidates D-Cache

+  */

+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)

+{

+  #if (__DCACHE_PRESENT == 1)

+    uint32_t ccsidr, sshift, wshift, sw;

+    uint32_t sets, ways;

+

+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache

+    ccsidr  = SCB->CCSIDR;

+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));

+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);

+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));

+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);

+

+    __DSB();

+

+    do {                                    // clean & invalidate D-Cache

+         uint32_t tmpways = ways;

+         do {

+              sw = ((tmpways << wshift) | (sets << sshift));

+              SCB->DCCISW = sw;

+            } while(tmpways--);

+        } while(sets--);

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/**

+  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)

+  \brief       D-Cache Invalidate by address

+  \param[in]   addr    address (aligned to 32-byte boundary)

+  \param[in]   dsize   size of memory block (in number of bytes)

+*/

+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

+{

+  #if (__DCACHE_PRESENT == 1)

+    int32_t  op_size = dsize;

+    uint32_t op_addr = (uint32_t)addr;

+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)

+

+    __DSB();

+

+    while (op_size > 0) {

+      SCB->DCIMVAC = op_addr;

+      op_addr +=          linesize;

+      op_size -= (int32_t)linesize;

+    }

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/**

+  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)

+  \brief       D-Cache Clean by address

+  \param[in]   addr    address (aligned to 32-byte boundary)

+  \param[in]   dsize   size of memory block (in number of bytes)

+*/

+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)

+{

+  #if (__DCACHE_PRESENT == 1)

+    int32_t  op_size = dsize;

+    uint32_t op_addr = (uint32_t) addr;

+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)

+

+    __DSB();

+

+    while (op_size > 0) {

+      SCB->DCCMVAC = op_addr;

+      op_addr +=          linesize;

+      op_size -= (int32_t)linesize;

+    }

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/**

+  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)

+  \brief       D-Cache Clean and Invalidate by address

+  \param[in]   addr    address (aligned to 32-byte boundary)

+  \param[in]   dsize   size of memory block (in number of bytes)

+*/

+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

+{

+  #if (__DCACHE_PRESENT == 1)

+    int32_t  op_size = dsize;

+    uint32_t op_addr = (uint32_t) addr;

+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)

+

+    __DSB();

+

+    while (op_size > 0) {

+      SCB->DCCIMVAC = op_addr;

+      op_addr +=          linesize;

+      op_size -= (int32_t)linesize;

+    }

+

+    __DSB();

+    __ISB();

+  #endif

+}

+

+

+/*@} end of CMSIS_Core_CacheFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */

+

+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

+  return (0UL);                                                     /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+/* ##################################### Debug In/Output function ########################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_core_DebugFunctions ITM Functions

+    \brief   Functions that access the ITM debug interface.

+  @{

+ */

+

+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

+

+

+/** \brief  ITM Send Character

+

+    The function transmits a character via the ITM channel 0, and

+    \li Just returns when no debugger is connected that has booked the output.

+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

+

+    \param [in]     ch  Character to transmit.

+

+    \returns            Character to transmit.

+ */

+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

+{

+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

+  {

+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }

+    ITM->PORT[0].u8 = (uint8_t)ch;

+  }

+  return (ch);

+}

+

+

+/** \brief  ITM Receive Character

+

+    The function inputs a character via the external variable \ref ITM_RxBuffer.

+

+    \return             Received character.

+    \return         -1  No character pending.

+ */

+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

+  int32_t ch = -1;                           /* no character available */

+

+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

+    ch = ITM_RxBuffer;

+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

+  }

+

+  return (ch);

+}

+

+

+/** \brief  ITM Check Character

+

+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

+

+    \return          0  No character available.

+    \return          1  Character available.

+ */

+__STATIC_INLINE int32_t ITM_CheckChar (void) {

+

+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

+    return (0);                                 /* no character available */

+  } else {

+    return (1);                                 /*    character available */

+  }

+}

+

+/*@} end of CMSIS_core_DebugFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM7_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

diff --git a/os/ext/CMSIS/include/core_cmFunc.h b/os/ext/CMSIS/include/core_cmFunc.h
index b5936735e..e0dbf7c54 100644
--- a/os/ext/CMSIS/include/core_cmFunc.h
+++ b/os/ext/CMSIS/include/core_cmFunc.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cmFunc.h

  * @brief    CMSIS Cortex-M Core Function Access Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2015 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -198,7 +198,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 }

 

 

-#if       (__CORTEX_M >= 0x03)

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

 

 /** \brief  Enable FIQ

 

@@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 }

 

 

+/** \brief  Set Base Priority with condition

+

+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+    or the new value increases the BASEPRI priority level.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)

+{

+  register uint32_t __regBasePriMax      __ASM("basepri_max");

+  __regBasePriMax = (basePri & 0xff);

+}

+

+

 /** \brief  Get Fault Mask

 

     This function returns the current value of the Fault Mask register.

@@ -267,10 +281,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
   __regFaultMask = (faultMask & (uint32_t)1);

 }

 

-#endif /* (__CORTEX_M >= 0x03) */

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

 

 

-#if       (__CORTEX_M == 0x04)

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

 

 /** \brief  Get FPSCR

 

@@ -303,19 +317,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 #endif

 }

 

-#endif /* (__CORTEX_M == 0x04) */

-

-

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

-

-#include <cmsis_iar.h>

-

-

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

-

-#include <cmsis_ccs.h>

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

 

 

 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

@@ -530,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
 {

   uint32_t result;

 

-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );

+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

   return(result);

 }

 

@@ -547,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
 }

 

 

+/** \brief  Set Base Priority with condition

+

+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+	or the new value increases the BASEPRI priority level.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)

+{

+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");

+}

+

+

 /** \brief  Get Fault Mask

 

     This function returns the current value of the Fault Mask register.

@@ -576,7 +591,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
 #endif /* (__CORTEX_M >= 0x03) */

 

 

-#if       (__CORTEX_M == 0x04)

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

 

 /** \brief  Get FPSCR

 

@@ -619,21 +634,34 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
 #endif

 }

 

-#endif /* (__CORTEX_M == 0x04) */

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

 

 

 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

 /* TASKING carm specific functions */

-

 /*

  * The CMSIS functions have been implemented as intrinsics in the compiler.

- * Please use "carm -?i" to get an up to date list of all instrinsics,

+ * Please use "carm -?i" to get an up to date list of all intrinsics,

  * Including the CMSIS ones.

  */

 

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

 #endif

 

 /*@} end of CMSIS_Core_RegAccFunctions */

 

-

 #endif /* __CORE_CMFUNC_H */

diff --git a/os/ext/CMSIS/include/core_cmInstr.h b/os/ext/CMSIS/include/core_cmInstr.h
index 8946c2c49..c8e045f56 100644
--- a/os/ext/CMSIS/include/core_cmInstr.h
+++ b/os/ext/CMSIS/include/core_cmInstr.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

  * @file     core_cmInstr.h

  * @brief    CMSIS Cortex-M Core Instruction Access Header File

- * @version  V3.20

- * @date     05. March 2013

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2014 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -89,24 +89,33 @@
     so that all instructions following the ISB are fetched from cache or

     memory, after the instruction has been completed.

  */

-#define __ISB()                           __isb(0xF)

-

+#define __ISB() do {\

+                   __schedule_barrier();\

+                   __isb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

 

 /** \brief  Data Synchronization Barrier

 

     This function acts as a special kind of Data Memory Barrier.

     It completes when all explicit memory accesses before this instruction complete.

  */

-#define __DSB()                           __dsb(0xF)

-

+#define __DSB() do {\

+                   __schedule_barrier();\

+                   __dsb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

 

 /** \brief  Data Memory Barrier

 

     This function ensures the apparent order of the explicit memory operations before

     and after the instruction, without ensuring their completion.

  */

-#define __DMB()                           __dmb(0xF)

-

+#define __DMB() do {\

+                   __schedule_barrier();\

+                   __dmb(0xF);\

+                   __schedule_barrier();\

+                } while (0)

 

 /** \brief  Reverse byte order (32 bit)

 

@@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 #define __BKPT(value)                       __breakpoint(value)

 

 

-#if       (__CORTEX_M >= 0x03)

-

 /** \brief  Reverse bit order of value

 

     This function reverses the bit order of the given value.

@@ -180,12 +187,42 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  Value to reverse

     \return               Reversed value

  */

-#define __RBIT                            __rbit

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+  #define __RBIT                          __rbit

+#else

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end

+

+  result = value;                      // r will be reversed bits of v; first get LSB of v

+  for (value >>= 1; value; value >>= 1)

+  {

+    result <<= 1;

+    result |= value & 1;

+    s--;

+  }

+  result <<= s;                       // shift when v's highest bits are zero

+  return(result);

+}

+#endif

+

 

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ                             __clz

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

 

 /** \brief  LDR Exclusive (8 bit)

 

-    This function performs a exclusive LDR command for 8 bit value.

+    This function executes a exclusive LDR instruction for 8 bit value.

 

     \param [in]    ptr  Pointer to data

     \return             value of type uint8_t at (*ptr)

@@ -195,7 +232,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

 /** \brief  LDR Exclusive (16 bit)

 

-    This function performs a exclusive LDR command for 16 bit values.

+    This function executes a exclusive LDR instruction for 16 bit values.

 

     \param [in]    ptr  Pointer to data

     \return        value of type uint16_t at (*ptr)

@@ -205,7 +242,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

 /** \brief  LDR Exclusive (32 bit)

 

-    This function performs a exclusive LDR command for 32 bit values.

+    This function executes a exclusive LDR instruction for 32 bit values.

 

     \param [in]    ptr  Pointer to data

     \return        value of type uint32_t at (*ptr)

@@ -215,7 +252,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

 /** \brief  STR Exclusive (8 bit)

 

-    This function performs a exclusive STR command for 8 bit values.

+    This function executes a exclusive STR instruction for 8 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

@@ -227,7 +264,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

 /** \brief  STR Exclusive (16 bit)

 

-    This function performs a exclusive STR command for 16 bit values.

+    This function executes a exclusive STR instruction for 16 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

@@ -239,7 +276,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

 /** \brief  STR Exclusive (32 bit)

 

-    This function performs a exclusive STR command for 32 bit values.

+    This function executes a exclusive STR instruction for 32 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

@@ -279,29 +316,83 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 #define __USAT                            __usat

 

 

-/** \brief  Count leading zeros

+/** \brief  Rotate Right with Extend (32 bit)

 

-    This function counts the number of leading zeros of a data value.

+    This function moves each bit of a bitstring right by one bit.

+    The carry input is shifted in at the left end of the bitstring.

 

-    \param [in]  value  Value to count the leading zeros

-    \return             number of leading zeros in value

+    \param [in]    value  Value to rotate

+    \return               Rotated value

  */

-#define __CLZ                             __clz

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

+{

+  rrx r0, r0

+  bx lr

+}

+#endif

 

-#endif /* (__CORTEX_M >= 0x03) */

 

+/** \brief  LDRT Unprivileged (8 bit)

 

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

 

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

 

-#include <cmsis_iar.h>

 

+/** \brief  LDRT Unprivileged (16 bit)

 

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

 

-#include <cmsis_ccs.h>

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRBT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRHT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRT(value, ptr)                __strt(value, ptr)

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

 

 

 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

@@ -322,7 +413,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 

     No Operation does nothing. This instruction can be used for code alignment purposes.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)

+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)

 {

   __ASM volatile ("nop");

 }

@@ -333,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
     Wait For Interrupt is a hint instruction that suspends execution

     until one of a number of events occurs.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)

+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)

 {

   __ASM volatile ("wfi");

 }

@@ -344,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
     Wait For Event is a hint instruction that permits the processor to enter

     a low-power state until one of a number of events occurs.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)

+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)

 {

   __ASM volatile ("wfe");

 }

@@ -354,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
 

     Send Event is a hint instruction. It causes an event to be signaled to the CPU.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)

+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)

 {

   __ASM volatile ("sev");

 }

@@ -366,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
     so that all instructions following the ISB are fetched from cache or

     memory, after the instruction has been completed.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)

+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)

 {

-  __ASM volatile ("isb");

+  __ASM volatile ("isb 0xF":::"memory");

 }

 

 

@@ -377,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
     This function acts as a special kind of Data Memory Barrier.

     It completes when all explicit memory accesses before this instruction complete.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)

+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)

 {

-  __ASM volatile ("dsb");

+  __ASM volatile ("dsb 0xF":::"memory");

 }

 

 

@@ -388,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
     This function ensures the apparent order of the explicit memory operations before

     and after the instruction, without ensuring their completion.

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)

+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)

 {

-  __ASM volatile ("dmb");

+  __ASM volatile ("dmb 0xF":::"memory");

 }

 

 

@@ -401,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
     \param [in]    value  Value to reverse

     \return               Reversed value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)

 {

 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

   return __builtin_bswap32(value);

@@ -421,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
     \param [in]    value  Value to reverse

     \return               Reversed value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)

 {

   uint32_t result;

 

@@ -437,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
     \param [in]    value  Value to reverse

     \return               Reversed value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)

+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)

 {

 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

   return (short)__builtin_bswap16(value);

@@ -458,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
     \param [in]    value  Number of Bits to rotate

     \return               Rotated value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

 {

-  return (op1 >> op2) | (op1 << (32 - op2)); 

+  return (op1 >> op2) | (op1 << (32 - op2));

 }

 

 

@@ -475,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
 #define __BKPT(value)                       __ASM volatile ("bkpt "#value)

 

 

-#if       (__CORTEX_M >= 0x03)

-

 /** \brief  Reverse bit order of value

 

     This function reverses the bit order of the given value.

@@ -484,23 +573,48 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
     \param [in]    value  Value to reverse

     \return               Reversed value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

 {

   uint32_t result;

 

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

-   return(result);

+#else

+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end

+

+  result = value;                      // r will be reversed bits of v; first get LSB of v

+  for (value >>= 1; value; value >>= 1)

+  {

+    result <<= 1;

+    result |= value & 1;

+    s--;

+  }

+  result <<= s;                       // shift when v's highest bits are zero

+#endif

+  return(result);

 }

 

 

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ             __builtin_clz

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

 /** \brief  LDR Exclusive (8 bit)

 

-    This function performs a exclusive LDR command for 8 bit value.

+    This function executes a exclusive LDR instruction for 8 bit value.

 

     \param [in]    ptr  Pointer to data

     \return             value of type uint8_t at (*ptr)

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

 {

     uint32_t result;

 

@@ -512,18 +626,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
     */

    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

 #endif

-   return(result);

+   return ((uint8_t) result);    /* Add explicit type cast here */

 }

 

 

 /** \brief  LDR Exclusive (16 bit)

 

-    This function performs a exclusive LDR command for 16 bit values.

+    This function executes a exclusive LDR instruction for 16 bit values.

 

     \param [in]    ptr  Pointer to data

     \return        value of type uint16_t at (*ptr)

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

 {

     uint32_t result;

 

@@ -535,18 +649,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
     */

    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

 #endif

-   return(result);

+   return ((uint16_t) result);    /* Add explicit type cast here */

 }

 

 

 /** \brief  LDR Exclusive (32 bit)

 

-    This function performs a exclusive LDR command for 32 bit values.

+    This function executes a exclusive LDR instruction for 32 bit values.

 

     \param [in]    ptr  Pointer to data

     \return        value of type uint32_t at (*ptr)

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

 {

     uint32_t result;

 

@@ -557,50 +671,50 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
 

 /** \brief  STR Exclusive (8 bit)

 

-    This function performs a exclusive STR command for 8 bit values.

+    This function executes a exclusive STR instruction for 8 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

     \return          0  Function succeeded

     \return          1  Function failed

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

 {

    uint32_t result;

 

-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

    return(result);

 }

 

 

 /** \brief  STR Exclusive (16 bit)

 

-    This function performs a exclusive STR command for 16 bit values.

+    This function executes a exclusive STR instruction for 16 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

     \return          0  Function succeeded

     \return          1  Function failed

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

 {

    uint32_t result;

 

-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

    return(result);

 }

 

 

 /** \brief  STR Exclusive (32 bit)

 

-    This function performs a exclusive STR command for 32 bit values.

+    This function executes a exclusive STR instruction for 32 bit values.

 

     \param [in]  value  Value to store

     \param [in]    ptr  Pointer to location

     \return          0  Function succeeded

     \return          1  Function failed

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

 {

    uint32_t result;

 

@@ -614,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
     This function removes the exclusive lock which is created by LDREX.

 

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)

+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)

 {

   __ASM volatile ("clrex" ::: "memory");

 }

@@ -652,35 +766,149 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
  })

 

 

-/** \brief  Count leading zeros

+/** \brief  Rotate Right with Extend (32 bit)

 

-    This function counts the number of leading zeros of a data value.

+    This function moves each bit of a bitstring right by one bit.

+    The carry input is shifted in at the left end of the bitstring.

 

-    \param [in]  value  Value to count the leading zeros

-    \return             number of leading zeros in value

+    \param [in]    value  Value to rotate

+    \return               Rotated value

  */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)

 {

-   uint32_t result;

+  uint32_t result;

 

-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );

+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

   return(result);

 }

 

-#endif /* (__CORTEX_M >= 0x03) */

 

+/** \brief  LDRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

 

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)

+{

+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)

+{

+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)

+{

+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );

+}

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

 

 

 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

 /* TASKING carm specific functions */

-

 /*

  * The CMSIS functions have been implemented as intrinsics in the compiler.

  * Please use "carm -?i" to get an up to date list of all intrinsics,

  * Including the CMSIS ones.

  */

 

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

 #endif

 

 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */

diff --git a/os/ext/CMSIS/include/core_cm4_simd.h b/os/ext/CMSIS/include/core_cmSimd.h
index af1831ee1..fd7214ee1 100644
--- a/os/ext/CMSIS/include/core_cm4_simd.h
+++ b/os/ext/CMSIS/include/core_cmSimd.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**

- * @file     core_cm4_simd.h

- * @brief    CMSIS Cortex-M4 SIMD Header File

- * @version  V3.20

- * @date     25. February 2013

+ * @file     core_cmSimd.h

+ * @brief    CMSIS Cortex-M SIMD Header File

+ * @version  V4.10

+ * @date     18. March 2015

  *

  * @note

  *

  ******************************************************************************/

-/* Copyright (c) 2009 - 2013 ARM LIMITED

+/* Copyright (c) 2009 - 2014 ARM LIMITED

 

    All rights reserved.

    Redistribution and use in source and binary forms, with or without

@@ -35,13 +35,17 @@
    ---------------------------------------------------------------------------*/

 

 

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CMSIMD_H

+#define __CORE_CMSIMD_H

+

 #ifdef __cplusplus

  extern "C" {

 #endif

 

-#ifndef __CORE_CM4_SIMD_H

-#define __CORE_CM4_SIMD_H

-

 

 /*******************************************************************************

  *                Hardware Abstraction Layer

@@ -56,8 +60,6 @@
 

 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

 /* ARM armcc specific functions */

-

-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

 #define __SADD8                           __sadd8

 #define __QADD8                           __qadd8

 #define __SHADD8                          __shadd8

@@ -127,34 +129,9 @@
 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

                                                       ((int64_t)(ARG3) << 32)      ) >> 32))

 

-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

-

-

-

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

-

-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

-#include <cmsis_iar.h>

-

-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

-

-

-

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

-

-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

-#include <cmsis_ccs.h>

-

-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

-

-

 

 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

 /* GNU gcc specific functions */

-

-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

 {

   uint32_t result;

@@ -539,19 +516,39 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t o
   return(result);

 }

 

-#define __SMLALD(ARG1,ARG2,ARG3) \

-({ \

-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

- })

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

 

-#define __SMLALDX(ARG1,ARG2,ARG3) \

-({ \

-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

- })

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

 

 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

 {

@@ -585,19 +582,39 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t o
   return(result);

 }

 

-#define __SMLSLD(ARG1,ARG2,ARG3) \

-({ \

-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

- })

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

 

-#define __SMLSLDX(ARG1,ARG2,ARG3) \

-({ \

-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

- })

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

 

 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

 {

@@ -648,26 +665,33 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1
  return(result);

 }

 

-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

 

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

 

 

-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

-/* TASKING carm specific functions */

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

 

 

-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

 /* not yet supported */

-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

 

 

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

 #endif

 

 /*@} end of group CMSIS_SIMD_intrinsics */

 

 

-#endif /* __CORE_CM4_SIMD_H */

-

 #ifdef __cplusplus

 }

 #endif

+

+#endif /* __CORE_CMSIMD_H */

diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h b/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
index bd0d1916d..61a388d9d 100644
--- a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
@@ -49,7 +49,7 @@
 /*

  * MCU type as defined in the ST header.

  */

-#define STM32F407xx

+#define STM32F746xx

 

 /*

  * IO pins assignments.

diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
index e878e5737..7c0a6e331 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -161,7 +161,6 @@
  * @brief   Maximum SPI/I2S clock frequency.

  */

 #define STM32_SPII2S_MAX        54000000

-#endif

 /** @} */

 

 /**

@@ -621,14 +620,12 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if defined(STM32F7xx) || defined(__DOXYGEN__)

 /*

  * Configuration-related checks.

  */

 #if !defined(STM32F7xx_MCUCONF)

 #error "Using a wrong mcuconf.h file, STM32F7xx_MCUCONF not defined"

 #endif

-#endif

 

 /**

  * @brief   Maximum frequency thresholds and wait states for flash access.

@@ -738,6 +735,7 @@
 

 #if STM32_HSECLK == 0

 #error "HSE frequency not defined"

+

 #elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)

 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"

 #endif

@@ -840,8 +838,10 @@
  */

 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

 #define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)

+

 #elif STM32_PLLSRC == STM32_PLLSRC_HSI

 #define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)

+

 #else

 #error "invalid STM32_PLLSRC value specified"

 #endif

@@ -884,12 +884,16 @@
  */

 #if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLP                  (0 << 16)

+

 #elif STM32_PLLP_VALUE == 4

 #define STM32_PLLP                  (1 << 16)

+

 #elif STM32_PLLP_VALUE == 6

 #define STM32_PLLP                  (2 << 16)

+

 #elif STM32_PLLP_VALUE == 8

 #define STM32_PLLP                  (3 << 16)

+

 #else

 #error "invalid STM32_PLLP_VALUE value specified"

 #endif

@@ -938,12 +942,16 @@
  */

 #if STM32_NO_INIT || defined(__DOXYGEN__)

 #define STM32_SYSCLK                STM32_HSICLK

+

 #elif (STM32_SW == STM32_SW_HSI)

 #define STM32_SYSCLK                STM32_HSICLK

+

 #elif (STM32_SW == STM32_SW_HSE)

 #define STM32_SYSCLK                STM32_HSECLK

+

 #elif (STM32_SW == STM32_SW_PLL)

 #define STM32_SYSCLK                STM32_PLL_P_CLKOUT

+

 #else

 #error "invalid STM32_SW value specified"

 #endif

@@ -957,12 +965,15 @@
 #if STM32_SYSCLK <= 144000000

 #define STM32_VOS                   STM32_VOS_SCALE3

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #elif STM32_SYSCLK <= 168000000

 #define STM32_VOS                   STM32_VOS_SCALE2

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #elif STM32_SYSCLK <= 180000000

 #define STM32_VOS                   STM32_VOS_SCALE1

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #else

 #define STM32_VOS                   STM32_VOS_SCALE1

 #define STM32_OVERDRIVE_REQUIRED    TRUE

@@ -973,22 +984,31 @@
  */

 #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_HCLK                  (STM32_SYSCLK / 1)

+

 #elif STM32_HPRE == STM32_HPRE_DIV2

 #define STM32_HCLK                  (STM32_SYSCLK / 2)

+

 #elif STM32_HPRE == STM32_HPRE_DIV4

 #define STM32_HCLK                  (STM32_SYSCLK / 4)

+

 #elif STM32_HPRE == STM32_HPRE_DIV8

 #define STM32_HCLK                  (STM32_SYSCLK / 8)

+

 #elif STM32_HPRE == STM32_HPRE_DIV16

 #define STM32_HCLK                  (STM32_SYSCLK / 16)

+

 #elif STM32_HPRE == STM32_HPRE_DIV64

 #define STM32_HCLK                  (STM32_SYSCLK / 64)

+

 #elif STM32_HPRE == STM32_HPRE_DIV128

 #define STM32_HCLK                  (STM32_SYSCLK / 128)

+

 #elif STM32_HPRE == STM32_HPRE_DIV256

 #define STM32_HCLK                  (STM32_SYSCLK / 256)

+

 #elif STM32_HPRE == STM32_HPRE_DIV512

 #define STM32_HCLK                  (STM32_SYSCLK / 512)

+

 #else

 #error "invalid STM32_HPRE value specified"

 #endif

@@ -1005,14 +1025,19 @@
  */

 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

 #define STM32_PCLK1                 (STM32_HCLK / 1)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV2

 #define STM32_PCLK1                 (STM32_HCLK / 2)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV4

 #define STM32_PCLK1                 (STM32_HCLK / 4)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV8

 #define STM32_PCLK1                 (STM32_HCLK / 8)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV16

 #define STM32_PCLK1                 (STM32_HCLK / 16)

+

 #else

 #error "invalid STM32_PPRE1 value specified"

 #endif

@@ -1029,14 +1054,19 @@
  */

 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

 #define STM32_PCLK2                 (STM32_HCLK / 1)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV2

 #define STM32_PCLK2                 (STM32_HCLK / 2)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV4

 #define STM32_PCLK2                 (STM32_HCLK / 4)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV8

 #define STM32_PCLK2                 (STM32_HCLK / 8)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV16

 #define STM32_PCLK2                 (STM32_HCLK / 16)

+

 #else

 #error "invalid STM32_PPRE2 value specified"

 #endif

@@ -1098,12 +1128,16 @@
  */

 #if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLI2SP               (0 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 4

 #define STM32_PLLI2SP               (1 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 6

 #define STM32_PLLI2SP               (2 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 8

 #define STM32_PLLI2SP               (3 << 16)

+

 #else

 #error "invalid STM32_PLLI2SP_VALUE value specified"

 #endif

@@ -1186,12 +1220,16 @@
  */

 #if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLSAIP               (0 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 4

 #define STM32_PLLSAIP               (1 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 6

 #define STM32_PLLSAIP               (2 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 8

 #define STM32_PLLSAIP               (3 << 16)

+

 #else

 #error "invalid STM32_PLLSAIP_VALUE value specified"

 #endif

@@ -1229,12 +1267,16 @@
  */

 #if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)

 #define STM32_MCO1DIVCLK             STM32_HSICLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_LSE

 #define STM32_MCO1DIVCLK             STM32_LSECLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_HSE

 #define STM32_MCO1DIVCLK             STM32_HSECLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_PLL

 #define STM32_MCO1DIVCLK             STM32_PLL_P_CLKOUT

+

 #else

 #error "invalid STM32_MCO1SEL value specified"

 #endif

@@ -1244,14 +1286,19 @@
  */

 #if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_MCO1CLK                STM32_MCO1DIVCLK

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 2)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 3)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 4)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 5)

+

 #else

 #error "invalid STM32_MCO1PRE value specified"

 #endif

@@ -1261,12 +1308,16 @@
  */

 #if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)

 #define STM32_MCO2DIVCLK             STM32_HSECLK

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_PLL

 #define STM32_MCO2DIVCLK             STM32_PLL_P_CLKOUT

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK

 #define STM32_MCO2DIVCLK             STM32_SYSCLK

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S

 #define STM32_MCO2DIVCLK             STM32_PLLI2S

+

 #else

 #error "invalid STM32_MCO2SEL value specified"

 #endif

@@ -1276,14 +1327,19 @@
  */

 #if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_MCO2CLK                STM32_MCO2DIVCLK

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 2)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 3)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 4)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 5)

+

 #else

 #error "invalid STM32_MCO2PRE value specified"

 #endif

@@ -1313,12 +1369,16 @@
  */

 #if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)

 #define STM32_RTCCLK                0

+

 #elif STM32_RTCSEL == STM32_RTCSEL_LSE

 #define STM32_RTCCLK                STM32_LSECLK

+

 #elif STM32_RTCSEL == STM32_RTCSEL_LSI

 #define STM32_RTCCLK                STM32_LSICLK

+

 #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV

 #define STM32_RTCCLK                STM32_HSEDIVCLK

+

 #else

 #error "invalid STM32_RTCSEL value specified"

 #endif

@@ -1356,35 +1416,32 @@
  */

 #if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)

 #define STM32_FLASHBITS             0x00000000

+

 #elif STM32_HCLK <= STM32_1WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000001

+

 #elif STM32_HCLK <= STM32_2WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000002

+

 #elif STM32_HCLK <= STM32_3WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000003

+

 #elif STM32_HCLK <= STM32_4WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000004

+

 #elif STM32_HCLK <= STM32_5WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000005

+

 #elif STM32_HCLK <= STM32_6WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000006

+

 #elif STM32_HCLK <= STM32_7WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000007

+

 #else

 #define STM32_FLASHBITS             0x00000008

 #endif

 

-/* There are differences in vector names in the various sub-families,

-   normalizing.*/

-#if 0

-#define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn

-#define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn

-#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn

-#define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn

-#define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn

-#define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn

-#endif

-

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -1399,8 +1456,7 @@
 

 /* Various helpers.*/

 #include "nvic.h"

-#include "stm32_isr.h"

-#include "stm32_dma.h"

+//#include "stm32_dma.h"

 #include "stm32_rcc.h"

 

 #ifdef __cplusplus

diff --git a/os/hal/ports/STM32/STM32F7xx/platform.mk b/os/hal/ports/STM32/STM32F7xx/platform.mk
index 3af296921..b03f9a91e 100644
--- a/os/hal/ports/STM32/STM32F7xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F7xx/platform.mk
@@ -4,8 +4,9 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))
 

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c \

-               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c

+#               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \

+

 ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c

 endif

@@ -85,6 +86,7 @@ endif
 

 # Required include directories

 PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \

+               $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \

diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
new file mode 100644
index 000000000..5b24de152
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
@@ -0,0 +1,1555 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32F7xx/stm32_rcc.h

+ * @brief   RCC helper driver header.

+ * @note    This file requires definitions from the ST header file

+ *          @p stm32f4xx.h.

+ *

+ * @addtogroup STM32F7xx_RCC

+ * @{

+ */

+#ifndef _STM32_RCC_

+#define _STM32_RCC_

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @name    Generic RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the clock of one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAPB1(mask, lp) {                                           \

+  RCC->APB1ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->APB1LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAPB1(mask, lp) {                                          \

+  RCC->APB1ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->APB1LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAPB1(mask) {                                                \

+  RCC->APB1RSTR |= (mask);                                                  \

+  RCC->APB1RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAPB2(mask, lp) {                                           \

+  RCC->APB2ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->APB2LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAPB2(mask, lp) {                                          \

+  RCC->APB2ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->APB2LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAPB2(mask) {                                                \

+  RCC->APB2RSTR |= (mask);                                                  \

+  RCC->APB2RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB1(mask, lp) {                                           \

+  RCC->AHB1ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB1LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB1(mask, lp) {                                          \

+  RCC->AHB1ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB1LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB1(mask) {                                                \

+  RCC->AHB1RSTR |= (mask);                                                  \

+  RCC->AHB1RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB2(mask, lp) {                                           \

+  RCC->AHB2ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB2LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB2(mask, lp) {                                          \

+  RCC->AHB2ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB2LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB2(mask) {                                                \

+  RCC->AHB2RSTR |= (mask);                                                  \

+  RCC->AHB2RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB3(mask, lp) {                                           \

+  RCC->AHB3ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB3LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB3(mask, lp) {                                          \

+  RCC->AHB3ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB3LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB3(mask) {                                                \

+  RCC->AHB3RSTR |= (mask);                                                  \

+  RCC->AHB3RSTR = 0;                                                        \

+}

+/** @} */

+

+/**

+ * @name    ADC peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the ADC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)

+

+/**

+ * @brief   Disables the ADC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)

+

+/**

+ * @brief   Resets the ADC1 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)

+

+/**

+ * @brief   Enables the ADC2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)

+

+/**

+ * @brief   Disables the ADC2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp)

+

+/**

+ * @brief   Resets the ADC2 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)

+

+/**

+ * @brief   Enables the ADC3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)

+

+/**

+ * @brief   Disables the ADC3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp)

+

+/**

+ * @brief   Resets the ADC3 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)

+/** @} */

+

+/**

+ * @name    DAC peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DAC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)

+

+/**

+ * @brief   Disables the DAC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)

+

+/**

+ * @brief   Resets the DAC1 peripheral.

+ *

+ * @api

+ */

+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)

+/** @} */

+

+/**

+ * @name    DMA peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DMA1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)

+

+/**

+ * @brief   Disables the DMA1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)

+

+/**

+ * @brief   Resets the DMA1 peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)

+

+/**

+ * @brief   Enables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)

+

+/**

+ * @brief   Disables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)

+

+/**

+ * @brief   Resets the DMA2 peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)

+/** @} */

+

+/**

+ * @name    BKPSRAM specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the BKPSRAM peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)

+

+/**

+ * @brief   Disables the BKPSRAM peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)

+/** @} */

+

+/**

+ * @name    PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)

+/** @} */

+

+

+/**

+ * @name    CAN peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Disables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Resets the CAN1 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)

+

+/**

+ * @brief   Enables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Disables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Resets the CAN2 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)

+/** @} */

+

+/**

+ * @name    ETH peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the ETH peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN |               \

+                                       RCC_AHB1ENR_ETHMACTXEN |             \

+                                       RCC_AHB1ENR_ETHMACRXEN, lp)

+

+/**

+ * @brief   Disables the ETH peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN |             \

+                                         RCC_AHB1ENR_ETHMACTXEN |           \

+                                         RCC_AHB1ENR_ETHMACRXEN, lp)

+

+/**

+ * @brief   Resets the ETH peripheral.

+ *

+ * @api

+ */

+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)

+/** @} */

+

+/**

+ * @name    I2C peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the I2C1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)

+

+/**

+ * @brief   Disables the I2C1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)

+

+/**

+ * @brief   Resets the I2C1 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)

+

+/**

+ * @brief   Enables the I2C2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)

+

+/**

+ * @brief   Disables the I2C2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)

+

+/**

+ * @brief   Resets the I2C2 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)

+

+/**

+ * @brief   Enables the I2C3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)

+

+/**

+ * @brief   Disables the I2C3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)

+

+/**

+ * @brief   Resets the I2C3 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)

+/** @} */

+

+/**

+ * @name    OTG peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the OTG_FS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)

+

+/**

+ * @brief   Disables the OTG_FS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp)

+

+/**

+ * @brief   Resets the OTG_FS peripheral.

+ *

+ * @api

+ */

+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)

+

+/**

+ * @brief   Enables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)

+

+/**

+ * @brief   Disables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp)

+

+/**

+ * @brief   Resets the OTG_HS peripheral.

+ *

+ * @api

+ */

+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)

+

+/**

+ * @brief   Enables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)

+

+/**

+ * @brief   Disables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)

+/** @} */

+

+/**

+ * @name    SDIO peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Disables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Resets the SDIO peripheral.

+ * @note    Not supported in this family, does nothing.

+ *

+ * @api

+ */

+#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)

+/** @} */

+

+/**

+ * @name    SPI peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the SPI1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)

+

+/**

+ * @brief   Disables the SPI1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)

+

+/**

+ * @brief   Resets the SPI1 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)

+

+/**

+ * @brief   Enables the SPI2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)

+

+/**

+ * @brief   Disables the SPI2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)

+

+/**

+ * @brief   Resets the SPI2 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)

+

+/**

+ * @brief   Enables the SPI3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)

+

+/**

+ * @brief   Disables the SPI3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)

+

+/**

+ * @brief   Resets the SPI3 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)

+

+/**

+ * @brief   Enables the SPI4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)

+

+/**

+ * @brief   Disables the SPI4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp)

+

+/**

+ * @brief   Resets the SPI4 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)

+

+/**

+ * @brief   Enables the SPI5 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)

+

+/**

+ * @brief   Disables the SPI5 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp)

+

+/**

+ * @brief   Resets the SPI5 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)

+

+/**

+ * @brief   Enables the SPI6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)

+

+/**

+ * @brief   Disables the SPI6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp)

+

+/**

+ * @brief   Resets the SPI6 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)

+/** @} */

+

+/**

+ * @name    TIM peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the TIM1 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)

+

+/**

+ * @brief   Disables the TIM1 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)

+

+/**

+ * @brief   Resets the TIM1 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)

+

+/**

+ * @brief   Enables the TIM2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)

+

+/**

+ * @brief   Disables the TIM2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)

+

+/**

+ * @brief   Resets the TIM2 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)

+

+/**

+ * @brief   Enables the TIM3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)

+

+/**

+ * @brief   Disables the TIM3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)

+

+/**

+ * @brief   Resets the TIM3 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)

+

+/**

+ * @brief   Enables the TIM4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)

+

+/**

+ * @brief   Disables the TIM4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)

+

+/**

+ * @brief   Resets the TIM4 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)

+

+/**

+ * @brief   Enables the TIM5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)

+

+/**

+ * @brief   Disables the TIM5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)

+

+/**

+ * @brief   Resets the TIM5 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)

+

+/**

+ * @brief   Enables the TIM6 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)

+

+/**

+ * @brief   Disables the TIM6 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)

+

+/**

+ * @brief   Resets the TIM6 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)

+

+/**

+ * @brief   Enables the TIM7 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)

+

+/**

+ * @brief   Disables the TIM7 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)

+

+/**

+ * @brief   Resets the TIM7 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)

+

+/**

+ * @brief   Enables the TIM8 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)

+

+/**

+ * @brief   Disables the TIM8 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)

+

+/**

+ * @brief   Resets the TIM8 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)

+

+/**

+ * @brief   Enables the TIM9peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)

+

+/**

+ * @brief   Disables the TIM9 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)

+

+/**

+ * @brief   Resets the TIM9 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)

+

+/**

+ * @brief   Enables the TIM10 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)

+

+/**

+ * @brief   Disables the TIM10 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)

+

+/**

+ * @brief   Resets the TIM10 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)

+

+/**

+ * @brief   Enables the TIM11 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)

+

+/**

+ * @brief   Disables the TIM11 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)

+

+/**

+ * @brief   Resets the TIM11 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)

+

+/**

+ * @brief   Enables the TIM12 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)

+

+/**

+ * @brief   Disables the TIM12 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)

+

+/**

+ * @brief   Resets the TIM12 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)

+

+/**

+ * @brief   Enables the TIM13 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)

+

+/**

+ * @brief   Disables the TIM13 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)

+

+/**

+ * @brief   Resets the TIM13 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)

+

+/**

+ * @brief   Enables the TIM14 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)

+

+/**

+ * @brief   Disables the TIM14 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)

+

+/**

+ * @brief   Resets the TIM14 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)

+/** @} */

+

+/**

+ * @name    USART/UART peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the USART1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)

+

+/**

+ * @brief   Disables the USART1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)

+

+/**

+ * @brief   Resets the USART1 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)

+

+/**

+ * @brief   Enables the USART2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)

+

+/**

+ * @brief   Disables the USART2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)

+

+/**

+ * @brief   Resets the USART2 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)

+

+/**

+ * @brief   Enables the USART3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)

+

+/**

+ * @brief   Disables the USART3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)

+

+/**

+ * @brief   Resets the USART3 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)

+

+/**

+ * @brief   Enables the USART6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)

+

+/**

+ * @brief   Disables the USART6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)

+

+/**

+ * @brief   Enables the UART4 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)

+

+/**

+ * @brief   Disables the UART4 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)

+

+/**

+ * @brief   Resets the UART4 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)

+

+/**

+ * @brief   Enables the UART5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)

+

+/**

+ * @brief   Disables the UART5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)

+

+/**

+ * @brief   Resets the UART5 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)

+

+/**

+ * @brief   Resets the USART6 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)

+/** @} */

+

+/**

+ * @name    LTDC peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the LTDC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)

+

+/**

+ * @brief   Disables the LTDC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp)

+

+/**

+ * @brief   Resets the LTDC peripheral.

+ *

+ * @api

+ */

+#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)

+

+/**

+ * @name    DMA2D peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Disables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Resets the DMA2D peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)

+/** @} */

+

+/**

+ * @name    FSMC peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the FSMC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)

+#else

+  #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)

+#endif

+

+/**

+ * @brief   Disables the FSMC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)

+#else

+  #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp)

+#endif

+

+/**

+ * @brief   Resets the FSMC peripheral.

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)

+#else

+  #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _STM32_RCC_ */

+

+/** @} */

diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
index 5e3d630a4..328ede9dd 100644
--- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
@@ -25,29 +25,6 @@
 #ifndef _STM32_REGISTRY_H_

 #define _STM32_REGISTRY_H_

 

-

-#if defined(STM32F439xx) || defined(STM32F429xx)

-#define STM32F429_439xx

-

-#elif defined(STM32F437xx) || defined(STM32F427xx)

-#define STM32F427_437xx

-

-#elif defined(STM32F405xx) || defined(STM32F415xx) ||                       \

-      defined(STM32F407xx) || defined(STM32F417xx)

-#define STM32F40_41xxx

-

-#elif defined(STM32F401xC) || defined(STM32F401xE)

-#define STM32F401xx

-

-#elif defined(STM32F411xE)

-#define STM32F411xx

-

-#elif defined(STM32F2XX)

-

-#else

-#error "STM32F2xx/F4xx device not specified"

-#endif

-

 /**

  * @brief   Sub-family identifier.

  */

@@ -64,9 +41,10 @@
  * @{

  */

 /*===========================================================================*/

-/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx.                       */

+/* STM32F745xx, STM32F746xx, STM32F756xx.                                    */

 /*===========================================================================*/

-#if defined(STM32F429_439xx) || defined(STM32F427_437xx)

+#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \

+    defined(__DOXYGEN__)

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

 #define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

@@ -348,746 +326,8 @@
 #define STM32_HAS_CRC                       TRUE

 #define STM32_CRC_PROGRAMMABLE              FALSE

 

-#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */

-

-/*===========================================================================*/

-/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F2XX.            */

-/*===========================================================================*/

-#if defined(STM32F40_41xxx) || defined(STM32F2XX)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      TRUE

-#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN                  0x00001100

-

-#define STM32_HAS_ADC3                      TRUE

-#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1))

-#define STM32_ADC3_DMA_CHN                  0x00000022

-

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      TRUE

-#define STM32_HAS_CAN2                      TRUE

-#define STM32_CAN_MAX_FILTERS               28

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  TRUE

-#define STM32_DAC1_CH1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_DAC1_CH1_DMA_CHN              0x00700000

-

-#define STM32_HAS_DAC1_CH2                  TRUE

-#define STM32_DAC1_CH2_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_DAC1_CH2_DMA_CHN              0x07000000

-

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#if defined(STM32F405xx) || defined(STM32F415xx)

-#define STM32_HAS_ETH                       FALSE

-#else

-#define STM32_HAS_ETH                       TRUE

-#endif

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     TRUE

-#define STM32_HAS_GPIOG                     TRUE

-#define STM32_HAS_GPIOI                     TRUE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN |          \

-                                             RCC_AHB1ENR_GPIOFEN |          \

-                                             RCC_AHB1ENR_GPIOGEN |          \

-                                             RCC_AHB1ENR_GPIOHEN |          \

-                                             RCC_AHB1ENR_GPIOIEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#if !defined(STM32F2XX)

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#else

-#define STM32_RTC_HAS_SUBSECONDS            FALSE

-#endif

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

+#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */

 

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      FALSE

-#define STM32_HAS_SPI5                      FALSE

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM6                      TRUE

-#define STM32_TIM6_IS_32BITS                FALSE

-#define STM32_TIM6_CHANNELS                 0

-

-#define STM32_HAS_TIM7                      TRUE

-#define STM32_TIM7_IS_32BITS                FALSE

-#define STM32_TIM7_CHANNELS                 0

-

-#define STM32_HAS_TIM8                      TRUE

-#define STM32_TIM8_IS_32BITS                FALSE

-#define STM32_TIM8_CHANNELS                 6

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM12                     TRUE

-#define STM32_TIM12_IS_32BITS               FALSE

-#define STM32_TIM12_CHANNELS                2

-

-#define STM32_HAS_TIM13                     TRUE

-#define STM32_TIM13_IS_32BITS               FALSE

-#define STM32_TIM13_CHANNELS                2

-

-#define STM32_HAS_TIM14                     TRUE

-#define STM32_TIM14_IS_32BITS               FALSE

-#define STM32_TIM14_CHANNELS                2

-

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    TRUE

-#define STM32_USART3_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 1)

-#define STM32_USART3_RX_DMA_CHN             0x00000040

-#define STM32_USART3_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_USART3_TX_DMA_CHN             0x00074000

-

-#define STM32_HAS_UART4                     TRUE

-#define STM32_UART4_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_UART4_RX_DMA_CHN              0x00000400

-#define STM32_UART4_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_UART4_TX_DMA_CHN              0x00040000

-

-#define STM32_HAS_UART5                     TRUE

-#define STM32_UART5_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)

-#define STM32_UART5_RX_DMA_CHN              0x00000004

-#define STM32_UART5_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_UART5_TX_DMA_CHN              0x40000000

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      TRUE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      TRUE

-#define STM32_FSMC_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_FSMC_DMA_CHN                  0x03010201

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */

-

-/*===========================================================================*/

-/* STM32F401xx.                                                              */

-/*===========================================================================*/

-#if defined(STM32F401xx)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      TRUE

-#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN                  0x00001100

-

-#define STM32_HAS_ADC3                      TRUE

-#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1))

-#define STM32_ADC3_DMA_CHN                  0x00000022

-

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      TRUE

-#define STM32_HAS_CAN2                      TRUE

-#define STM32_CAN_MAX_FILTERS               28

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  FALSE

-#define STM32_HAS_DAC1_CH2                  FALSE

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH                       FALSE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     FALSE

-#define STM32_HAS_GPIOG                     FALSE

-#define STM32_HAS_GPIOI                     FALSE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      TRUE

-#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_SPI4_RX_DMA_CHN               0x00005004

-#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_SPI4_TX_DMA_CHN               0x00050040

-

-#define STM32_HAS_SPI5                      FALSE

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM6                      FALSE

-#define STM32_HAS_TIM7                      FALSE

-#define STM32_HAS_TIM8                      FALSE

-#define STM32_HAS_TIM12                     FALSE

-#define STM32_HAS_TIM13                     FALSE

-#define STM32_HAS_TIM14                     FALSE

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    FALSE

-#define STM32_HAS_UART4                     FALSE

-#define STM32_HAS_UART5                     FALSE

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      FALSE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      FALSE

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif /* defined(STM32F401xx) */

-

-/*===========================================================================*/

-/* STM32F411xE.                                                              */

-/*===========================================================================*/

-#if defined(STM32F411xx)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      FALSE

-#define STM32_HAS_ADC3                      FALSE

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      FALSE

-#define STM32_HAS_CAN2                      FALSE

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  FALSE

-#define STM32_HAS_DAC1_CH2                  FALSE

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH                       FALSE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     FALSE

-#define STM32_HAS_GPIOG                     FALSE

-#define STM32_HAS_GPIOI                     FALSE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN |          \

-                                             RCC_AHB1ENR_GPIOHEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      TRUE

-#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_SPI4_RX_DMA_CHN               0x00005004

-#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_SPI4_TX_DMA_CHN               0x00050040

-

-#define STM32_HAS_SPI5                      TRUE

-#define STM32_SPI5_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI5_RX_DMA_CHN               0x00702000

-#define STM32_SPI5_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 4) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SPI5_TX_DMA_CHN               0x07020000

-

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM6                      FALSE

-#define STM32_HAS_TIM7                      FALSE

-#define STM32_HAS_TIM8                      FALSE

-#define STM32_HAS_TIM12                     FALSE

-#define STM32_HAS_TIM13                     FALSE

-#define STM32_HAS_TIM14                     FALSE

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    FALSE

-#define STM32_HAS_UART4                     FALSE

-#define STM32_HAS_UART5                     FALSE

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      FALSE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      FALSE

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif

 /** @} */

 

 #endif /* _STM32_REGISTRY_H_ */