diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 768 |
1 files changed, 4 insertions, 764 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index 5e3d630a4..328ede9dd 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -25,29 +25,6 @@ #ifndef _STM32_REGISTRY_H_
#define _STM32_REGISTRY_H_
-
-#if defined(STM32F439xx) || defined(STM32F429xx)
-#define STM32F429_439xx
-
-#elif defined(STM32F437xx) || defined(STM32F427xx)
-#define STM32F427_437xx
-
-#elif defined(STM32F405xx) || defined(STM32F415xx) || \
- defined(STM32F407xx) || defined(STM32F417xx)
-#define STM32F40_41xxx
-
-#elif defined(STM32F401xC) || defined(STM32F401xE)
-#define STM32F401xx
-
-#elif defined(STM32F411xE)
-#define STM32F411xx
-
-#elif defined(STM32F2XX)
-
-#else
-#error "STM32F2xx/F4xx device not specified"
-#endif
-
/**
* @brief Sub-family identifier.
*/
@@ -64,9 +41,10 @@ * @{
*/
/*===========================================================================*/
-/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
+/* STM32F745xx, STM32F746xx, STM32F756xx. */
/*===========================================================================*/
-#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
+#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \
+ defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
@@ -348,746 +326,8 @@ #define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE FALSE
-#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
-
-/*===========================================================================*/
-/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F2XX. */
-/*===========================================================================*/
-#if defined(STM32F40_41xxx) || defined(STM32F2XX)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 TRUE
-#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_DAC1_CH2_DMA_CHN 0x07000000
-
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#if defined(STM32F405xx) || defined(STM32F415xx)
-#define STM32_HAS_ETH FALSE
-#else
-#define STM32_HAS_ETH TRUE
-#endif
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI TRUE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#if !defined(STM32F2XX)
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#else
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#endif
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM8 TRUE
-#define STM32_TIM8_IS_32BITS FALSE
-#define STM32_TIM8_CHANNELS 6
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 2
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 2
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 2
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 2
-
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_UART5_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 TRUE
-#define STM32_HAS_OTG2 TRUE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC TRUE
-#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 5) |\
- STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_FSMC_DMA_CHN 0x03010201
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
-
-/*===========================================================================*/
-/* STM32F401xx. */
-/*===========================================================================*/
-#if defined(STM32F401xx)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 2
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 2
-
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 TRUE
-#define STM32_HAS_OTG2 FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F401xx) */
-
-/*===========================================================================*/
-/* STM32F411xE. */
-/*===========================================================================*/
-#if defined(STM32F411xx)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07020000
-
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 2
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 2
-
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 TRUE
-#define STM32_HAS_OTG2 FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif
/** @} */
#endif /* _STM32_REGISTRY_H_ */
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