git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8135 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 1635 insertions, 782 deletions

diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h b/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
index bd0d1916d..61a388d9d 100644
--- a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h
@@ -49,7 +49,7 @@
 /*

  * MCU type as defined in the ST header.

  */

-#define STM32F407xx

+#define STM32F746xx

 

 /*

  * IO pins assignments.

diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
index e878e5737..7c0a6e331 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -161,7 +161,6 @@
  * @brief   Maximum SPI/I2S clock frequency.

  */

 #define STM32_SPII2S_MAX        54000000

-#endif

 /** @} */

 

 /**

@@ -621,14 +620,12 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if defined(STM32F7xx) || defined(__DOXYGEN__)

 /*

  * Configuration-related checks.

  */

 #if !defined(STM32F7xx_MCUCONF)

 #error "Using a wrong mcuconf.h file, STM32F7xx_MCUCONF not defined"

 #endif

-#endif

 

 /**

  * @brief   Maximum frequency thresholds and wait states for flash access.

@@ -738,6 +735,7 @@
 

 #if STM32_HSECLK == 0

 #error "HSE frequency not defined"

+

 #elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)

 #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"

 #endif

@@ -840,8 +838,10 @@
  */

 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

 #define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)

+

 #elif STM32_PLLSRC == STM32_PLLSRC_HSI

 #define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)

+

 #else

 #error "invalid STM32_PLLSRC value specified"

 #endif

@@ -884,12 +884,16 @@
  */

 #if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLP                  (0 << 16)

+

 #elif STM32_PLLP_VALUE == 4

 #define STM32_PLLP                  (1 << 16)

+

 #elif STM32_PLLP_VALUE == 6

 #define STM32_PLLP                  (2 << 16)

+

 #elif STM32_PLLP_VALUE == 8

 #define STM32_PLLP                  (3 << 16)

+

 #else

 #error "invalid STM32_PLLP_VALUE value specified"

 #endif

@@ -938,12 +942,16 @@
  */

 #if STM32_NO_INIT || defined(__DOXYGEN__)

 #define STM32_SYSCLK                STM32_HSICLK

+

 #elif (STM32_SW == STM32_SW_HSI)

 #define STM32_SYSCLK                STM32_HSICLK

+

 #elif (STM32_SW == STM32_SW_HSE)

 #define STM32_SYSCLK                STM32_HSECLK

+

 #elif (STM32_SW == STM32_SW_PLL)

 #define STM32_SYSCLK                STM32_PLL_P_CLKOUT

+

 #else

 #error "invalid STM32_SW value specified"

 #endif

@@ -957,12 +965,15 @@
 #if STM32_SYSCLK <= 144000000

 #define STM32_VOS                   STM32_VOS_SCALE3

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #elif STM32_SYSCLK <= 168000000

 #define STM32_VOS                   STM32_VOS_SCALE2

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #elif STM32_SYSCLK <= 180000000

 #define STM32_VOS                   STM32_VOS_SCALE1

 #define STM32_OVERDRIVE_REQUIRED    FALSE

+

 #else

 #define STM32_VOS                   STM32_VOS_SCALE1

 #define STM32_OVERDRIVE_REQUIRED    TRUE

@@ -973,22 +984,31 @@
  */

 #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_HCLK                  (STM32_SYSCLK / 1)

+

 #elif STM32_HPRE == STM32_HPRE_DIV2

 #define STM32_HCLK                  (STM32_SYSCLK / 2)

+

 #elif STM32_HPRE == STM32_HPRE_DIV4

 #define STM32_HCLK                  (STM32_SYSCLK / 4)

+

 #elif STM32_HPRE == STM32_HPRE_DIV8

 #define STM32_HCLK                  (STM32_SYSCLK / 8)

+

 #elif STM32_HPRE == STM32_HPRE_DIV16

 #define STM32_HCLK                  (STM32_SYSCLK / 16)

+

 #elif STM32_HPRE == STM32_HPRE_DIV64

 #define STM32_HCLK                  (STM32_SYSCLK / 64)

+

 #elif STM32_HPRE == STM32_HPRE_DIV128

 #define STM32_HCLK                  (STM32_SYSCLK / 128)

+

 #elif STM32_HPRE == STM32_HPRE_DIV256

 #define STM32_HCLK                  (STM32_SYSCLK / 256)

+

 #elif STM32_HPRE == STM32_HPRE_DIV512

 #define STM32_HCLK                  (STM32_SYSCLK / 512)

+

 #else

 #error "invalid STM32_HPRE value specified"

 #endif

@@ -1005,14 +1025,19 @@
  */

 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

 #define STM32_PCLK1                 (STM32_HCLK / 1)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV2

 #define STM32_PCLK1                 (STM32_HCLK / 2)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV4

 #define STM32_PCLK1                 (STM32_HCLK / 4)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV8

 #define STM32_PCLK1                 (STM32_HCLK / 8)

+

 #elif STM32_PPRE1 == STM32_PPRE1_DIV16

 #define STM32_PCLK1                 (STM32_HCLK / 16)

+

 #else

 #error "invalid STM32_PPRE1 value specified"

 #endif

@@ -1029,14 +1054,19 @@
  */

 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

 #define STM32_PCLK2                 (STM32_HCLK / 1)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV2

 #define STM32_PCLK2                 (STM32_HCLK / 2)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV4

 #define STM32_PCLK2                 (STM32_HCLK / 4)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV8

 #define STM32_PCLK2                 (STM32_HCLK / 8)

+

 #elif STM32_PPRE2 == STM32_PPRE2_DIV16

 #define STM32_PCLK2                 (STM32_HCLK / 16)

+

 #else

 #error "invalid STM32_PPRE2 value specified"

 #endif

@@ -1098,12 +1128,16 @@
  */

 #if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLI2SP               (0 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 4

 #define STM32_PLLI2SP               (1 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 6

 #define STM32_PLLI2SP               (2 << 16)

+

 #elif STM32_PLLI2SP_VALUE == 8

 #define STM32_PLLI2SP               (3 << 16)

+

 #else

 #error "invalid STM32_PLLI2SP_VALUE value specified"

 #endif

@@ -1186,12 +1220,16 @@
  */

 #if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)

 #define STM32_PLLSAIP               (0 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 4

 #define STM32_PLLSAIP               (1 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 6

 #define STM32_PLLSAIP               (2 << 16)

+

 #elif STM32_PLLSAIP_VALUE == 8

 #define STM32_PLLSAIP               (3 << 16)

+

 #else

 #error "invalid STM32_PLLSAIP_VALUE value specified"

 #endif

@@ -1229,12 +1267,16 @@
  */

 #if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)

 #define STM32_MCO1DIVCLK             STM32_HSICLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_LSE

 #define STM32_MCO1DIVCLK             STM32_LSECLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_HSE

 #define STM32_MCO1DIVCLK             STM32_HSECLK

+

 #elif STM32_MCO1SEL == STM32_MCO1SEL_PLL

 #define STM32_MCO1DIVCLK             STM32_PLL_P_CLKOUT

+

 #else

 #error "invalid STM32_MCO1SEL value specified"

 #endif

@@ -1244,14 +1286,19 @@
  */

 #if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_MCO1CLK                STM32_MCO1DIVCLK

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 2)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 3)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 4)

+

 #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5

 #define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 5)

+

 #else

 #error "invalid STM32_MCO1PRE value specified"

 #endif

@@ -1261,12 +1308,16 @@
  */

 #if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)

 #define STM32_MCO2DIVCLK             STM32_HSECLK

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_PLL

 #define STM32_MCO2DIVCLK             STM32_PLL_P_CLKOUT

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK

 #define STM32_MCO2DIVCLK             STM32_SYSCLK

+

 #elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S

 #define STM32_MCO2DIVCLK             STM32_PLLI2S

+

 #else

 #error "invalid STM32_MCO2SEL value specified"

 #endif

@@ -1276,14 +1327,19 @@
  */

 #if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)

 #define STM32_MCO2CLK                STM32_MCO2DIVCLK

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 2)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 3)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 4)

+

 #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5

 #define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 5)

+

 #else

 #error "invalid STM32_MCO2PRE value specified"

 #endif

@@ -1313,12 +1369,16 @@
  */

 #if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)

 #define STM32_RTCCLK                0

+

 #elif STM32_RTCSEL == STM32_RTCSEL_LSE

 #define STM32_RTCCLK                STM32_LSECLK

+

 #elif STM32_RTCSEL == STM32_RTCSEL_LSI

 #define STM32_RTCCLK                STM32_LSICLK

+

 #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV

 #define STM32_RTCCLK                STM32_HSEDIVCLK

+

 #else

 #error "invalid STM32_RTCSEL value specified"

 #endif

@@ -1356,35 +1416,32 @@
  */

 #if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)

 #define STM32_FLASHBITS             0x00000000

+

 #elif STM32_HCLK <= STM32_1WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000001

+

 #elif STM32_HCLK <= STM32_2WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000002

+

 #elif STM32_HCLK <= STM32_3WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000003

+

 #elif STM32_HCLK <= STM32_4WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000004

+

 #elif STM32_HCLK <= STM32_5WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000005

+

 #elif STM32_HCLK <= STM32_6WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000006

+

 #elif STM32_HCLK <= STM32_7WS_THRESHOLD

 #define STM32_FLASHBITS             0x00000007

+

 #else

 #define STM32_FLASHBITS             0x00000008

 #endif

 

-/* There are differences in vector names in the various sub-families,

-   normalizing.*/

-#if 0

-#define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn

-#define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn

-#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn

-#define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn

-#define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn

-#define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn

-#endif

-

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -1399,8 +1456,7 @@
 

 /* Various helpers.*/

 #include "nvic.h"

-#include "stm32_isr.h"

-#include "stm32_dma.h"

+//#include "stm32_dma.h"

 #include "stm32_rcc.h"

 

 #ifdef __cplusplus

diff --git a/os/hal/ports/STM32/STM32F7xx/platform.mk b/os/hal/ports/STM32/STM32F7xx/platform.mk
index 3af296921..b03f9a91e 100644
--- a/os/hal/ports/STM32/STM32F7xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F7xx/platform.mk
@@ -4,8 +4,9 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))
 

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c \

-               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c

+#               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \

+

 ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c

 endif

@@ -85,6 +86,7 @@ endif
 

 # Required include directories

 PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \

+               $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \

diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
new file mode 100644
index 000000000..5b24de152
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
@@ -0,0 +1,1555 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32F7xx/stm32_rcc.h

+ * @brief   RCC helper driver header.

+ * @note    This file requires definitions from the ST header file

+ *          @p stm32f4xx.h.

+ *

+ * @addtogroup STM32F7xx_RCC

+ * @{

+ */

+#ifndef _STM32_RCC_

+#define _STM32_RCC_

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @name    Generic RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the clock of one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAPB1(mask, lp) {                                           \

+  RCC->APB1ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->APB1LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAPB1(mask, lp) {                                          \

+  RCC->APB1ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->APB1LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the APB1 bus.

+ *

+ * @param[in] mask      APB1 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAPB1(mask) {                                                \

+  RCC->APB1RSTR |= (mask);                                                  \

+  RCC->APB1RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAPB2(mask, lp) {                                           \

+  RCC->APB2ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->APB2LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAPB2(mask, lp) {                                          \

+  RCC->APB2ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->APB2LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the APB2 bus.

+ *

+ * @param[in] mask      APB2 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAPB2(mask) {                                                \

+  RCC->APB2RSTR |= (mask);                                                  \

+  RCC->APB2RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB1(mask, lp) {                                           \

+  RCC->AHB1ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB1LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB1(mask, lp) {                                          \

+  RCC->AHB1ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB1LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB1 bus.

+ *

+ * @param[in] mask      AHB1 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB1(mask) {                                                \

+  RCC->AHB1RSTR |= (mask);                                                  \

+  RCC->AHB1RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB2(mask, lp) {                                           \

+  RCC->AHB2ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB2LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB2(mask, lp) {                                          \

+  RCC->AHB2ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB2LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB2 bus.

+ *

+ * @param[in] mask      AHB2 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB2(mask) {                                                \

+  RCC->AHB2RSTR |= (mask);                                                  \

+  RCC->AHB2RSTR = 0;                                                        \

+}

+

+/**

+ * @brief   Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableAHB3(mask, lp) {                                           \

+  RCC->AHB3ENR |= (mask);                                                   \

+  if (lp)                                                                   \

+    RCC->AHB3LPENR |= (mask);                                               \

+}

+

+/**

+ * @brief   Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableAHB3(mask, lp) {                                          \

+  RCC->AHB3ENR &= ~(mask);                                                  \

+  if (lp)                                                                   \

+    RCC->AHB3LPENR &= ~(mask);                                              \

+}

+

+/**

+ * @brief   Resets one or more peripheral on the AHB3 (FSMC) bus.

+ *

+ * @param[in] mask      AHB3 peripherals mask

+ *

+ * @api

+ */

+#define rccResetAHB3(mask) {                                                \

+  RCC->AHB3RSTR |= (mask);                                                  \

+  RCC->AHB3RSTR = 0;                                                        \

+}

+/** @} */

+

+/**

+ * @name    ADC peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the ADC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)

+

+/**

+ * @brief   Disables the ADC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)

+

+/**

+ * @brief   Resets the ADC1 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)

+

+/**

+ * @brief   Enables the ADC2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)

+

+/**

+ * @brief   Disables the ADC2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp)

+

+/**

+ * @brief   Resets the ADC2 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)

+

+/**

+ * @brief   Enables the ADC3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)

+

+/**

+ * @brief   Disables the ADC3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp)

+

+/**

+ * @brief   Resets the ADC3 peripheral.

+ *

+ * @api

+ */

+#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)

+/** @} */

+

+/**

+ * @name    DAC peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DAC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)

+

+/**

+ * @brief   Disables the DAC1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)

+

+/**

+ * @brief   Resets the DAC1 peripheral.

+ *

+ * @api

+ */

+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)

+/** @} */

+

+/**

+ * @name    DMA peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DMA1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)

+

+/**

+ * @brief   Disables the DMA1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)

+

+/**

+ * @brief   Resets the DMA1 peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)

+

+/**

+ * @brief   Enables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)

+

+/**

+ * @brief   Disables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)

+

+/**

+ * @brief   Resets the DMA2 peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)

+/** @} */

+

+/**

+ * @name    BKPSRAM specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the BKPSRAM peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)

+

+/**

+ * @brief   Disables the BKPSRAM peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)

+/** @} */

+

+/**

+ * @name    PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)

+/** @} */

+

+

+/**

+ * @name    CAN peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Disables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Resets the CAN1 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)

+

+/**

+ * @brief   Enables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Disables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Resets the CAN2 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)

+/** @} */

+

+/**

+ * @name    ETH peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the ETH peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN |               \

+                                       RCC_AHB1ENR_ETHMACTXEN |             \

+                                       RCC_AHB1ENR_ETHMACRXEN, lp)

+

+/**

+ * @brief   Disables the ETH peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN |             \

+                                         RCC_AHB1ENR_ETHMACTXEN |           \

+                                         RCC_AHB1ENR_ETHMACRXEN, lp)

+

+/**

+ * @brief   Resets the ETH peripheral.

+ *

+ * @api

+ */

+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)

+/** @} */

+

+/**

+ * @name    I2C peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the I2C1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)

+

+/**

+ * @brief   Disables the I2C1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)

+

+/**

+ * @brief   Resets the I2C1 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)

+

+/**

+ * @brief   Enables the I2C2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)

+

+/**

+ * @brief   Disables the I2C2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)

+

+/**

+ * @brief   Resets the I2C2 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)

+

+/**

+ * @brief   Enables the I2C3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)

+

+/**

+ * @brief   Disables the I2C3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)

+

+/**

+ * @brief   Resets the I2C3 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)

+/** @} */

+

+/**

+ * @name    OTG peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the OTG_FS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)

+

+/**

+ * @brief   Disables the OTG_FS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp)

+

+/**

+ * @brief   Resets the OTG_FS peripheral.

+ *

+ * @api

+ */

+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)

+

+/**

+ * @brief   Enables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)

+

+/**

+ * @brief   Disables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp)

+

+/**

+ * @brief   Resets the OTG_HS peripheral.

+ *

+ * @api

+ */

+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)

+

+/**

+ * @brief   Enables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)

+

+/**

+ * @brief   Disables the OTG_HS peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)

+/** @} */

+

+/**

+ * @name    SDIO peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Disables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Resets the SDIO peripheral.

+ * @note    Not supported in this family, does nothing.

+ *

+ * @api

+ */

+#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)

+/** @} */

+

+/**

+ * @name    SPI peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the SPI1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)

+

+/**

+ * @brief   Disables the SPI1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)

+

+/**

+ * @brief   Resets the SPI1 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)

+

+/**

+ * @brief   Enables the SPI2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)

+

+/**

+ * @brief   Disables the SPI2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)

+

+/**

+ * @brief   Resets the SPI2 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)

+

+/**

+ * @brief   Enables the SPI3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)

+

+/**

+ * @brief   Disables the SPI3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)

+

+/**

+ * @brief   Resets the SPI3 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)

+

+/**

+ * @brief   Enables the SPI4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)

+

+/**

+ * @brief   Disables the SPI4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp)

+

+/**

+ * @brief   Resets the SPI4 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)

+

+/**

+ * @brief   Enables the SPI5 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)

+

+/**

+ * @brief   Disables the SPI5 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp)

+

+/**

+ * @brief   Resets the SPI5 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)

+

+/**

+ * @brief   Enables the SPI6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)

+

+/**

+ * @brief   Disables the SPI6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp)

+

+/**

+ * @brief   Resets the SPI6 peripheral.

+ *

+ * @api

+ */

+#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)

+/** @} */

+

+/**

+ * @name    TIM peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the TIM1 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)

+

+/**

+ * @brief   Disables the TIM1 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)

+

+/**

+ * @brief   Resets the TIM1 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)

+

+/**

+ * @brief   Enables the TIM2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)

+

+/**

+ * @brief   Disables the TIM2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)

+

+/**

+ * @brief   Resets the TIM2 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)

+

+/**

+ * @brief   Enables the TIM3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)

+

+/**

+ * @brief   Disables the TIM3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)

+

+/**

+ * @brief   Resets the TIM3 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)

+

+/**

+ * @brief   Enables the TIM4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)

+

+/**

+ * @brief   Disables the TIM4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)

+

+/**

+ * @brief   Resets the TIM4 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)

+

+/**

+ * @brief   Enables the TIM5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)

+

+/**

+ * @brief   Disables the TIM5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)

+

+/**

+ * @brief   Resets the TIM5 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)

+

+/**

+ * @brief   Enables the TIM6 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)

+

+/**

+ * @brief   Disables the TIM6 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)

+

+/**

+ * @brief   Resets the TIM6 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)

+

+/**

+ * @brief   Enables the TIM7 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)

+

+/**

+ * @brief   Disables the TIM7 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)

+

+/**

+ * @brief   Resets the TIM7 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)

+

+/**

+ * @brief   Enables the TIM8 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)

+

+/**

+ * @brief   Disables the TIM8 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)

+

+/**

+ * @brief   Resets the TIM8 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)

+

+/**

+ * @brief   Enables the TIM9peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)

+

+/**

+ * @brief   Disables the TIM9 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)

+

+/**

+ * @brief   Resets the TIM9 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)

+

+/**

+ * @brief   Enables the TIM10 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)

+

+/**

+ * @brief   Disables the TIM10 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)

+

+/**

+ * @brief   Resets the TIM10 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)

+

+/**

+ * @brief   Enables the TIM11 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)

+

+/**

+ * @brief   Disables the TIM11 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)

+

+/**

+ * @brief   Resets the TIM11 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)

+

+/**

+ * @brief   Enables the TIM12 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)

+

+/**

+ * @brief   Disables the TIM12 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)

+

+/**

+ * @brief   Resets the TIM12 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)

+

+/**

+ * @brief   Enables the TIM13 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)

+

+/**

+ * @brief   Disables the TIM13 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)

+

+/**

+ * @brief   Resets the TIM13 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)

+

+/**

+ * @brief   Enables the TIM14 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)

+

+/**

+ * @brief   Disables the TIM14 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)

+

+/**

+ * @brief   Resets the TIM14 peripheral.

+ *

+ * @api

+ */

+#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)

+/** @} */

+

+/**

+ * @name    USART/UART peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the USART1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)

+

+/**

+ * @brief   Disables the USART1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)

+

+/**

+ * @brief   Resets the USART1 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)

+

+/**

+ * @brief   Enables the USART2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)

+

+/**

+ * @brief   Disables the USART2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)

+

+/**

+ * @brief   Resets the USART2 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)

+

+/**

+ * @brief   Enables the USART3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)

+

+/**

+ * @brief   Disables the USART3 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)

+

+/**

+ * @brief   Resets the USART3 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)

+

+/**

+ * @brief   Enables the USART6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)

+

+/**

+ * @brief   Disables the USART6 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)

+

+/**

+ * @brief   Enables the UART4 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)

+

+/**

+ * @brief   Disables the UART4 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)

+

+/**

+ * @brief   Resets the UART4 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)

+

+/**

+ * @brief   Enables the UART5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)

+

+/**

+ * @brief   Disables the UART5 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)

+

+/**

+ * @brief   Resets the UART5 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)

+

+/**

+ * @brief   Resets the USART6 peripheral.

+ *

+ * @api

+ */

+#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)

+/** @} */

+

+/**

+ * @name    LTDC peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the LTDC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)

+

+/**

+ * @brief   Disables the LTDC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp)

+

+/**

+ * @brief   Resets the LTDC peripheral.

+ *

+ * @api

+ */

+#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)

+

+/**

+ * @name    DMA2D peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Disables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Resets the DMA2D peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)

+/** @} */

+

+/**

+ * @name    FSMC peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the FSMC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)

+#else

+  #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)

+#endif

+

+/**

+ * @brief   Disables the FSMC peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)

+#else

+  #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp)

+#endif

+

+/**

+ * @brief   Resets the FSMC peripheral.

+ *

+ * @api

+ */

+#if defined(STM32_FSMC_IS_FMC)

+  #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)

+#else

+  #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _STM32_RCC_ */

+

+/** @} */

diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
index 5e3d630a4..328ede9dd 100644
--- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
@@ -25,29 +25,6 @@
 #ifndef _STM32_REGISTRY_H_

 #define _STM32_REGISTRY_H_

 

-

-#if defined(STM32F439xx) || defined(STM32F429xx)

-#define STM32F429_439xx

-

-#elif defined(STM32F437xx) || defined(STM32F427xx)

-#define STM32F427_437xx

-

-#elif defined(STM32F405xx) || defined(STM32F415xx) ||                       \

-      defined(STM32F407xx) || defined(STM32F417xx)

-#define STM32F40_41xxx

-

-#elif defined(STM32F401xC) || defined(STM32F401xE)

-#define STM32F401xx

-

-#elif defined(STM32F411xE)

-#define STM32F411xx

-

-#elif defined(STM32F2XX)

-

-#else

-#error "STM32F2xx/F4xx device not specified"

-#endif

-

 /**

  * @brief   Sub-family identifier.

  */

@@ -64,9 +41,10 @@
  * @{

  */

 /*===========================================================================*/

-/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx.                       */

+/* STM32F745xx, STM32F746xx, STM32F756xx.                                    */

 /*===========================================================================*/

-#if defined(STM32F429_439xx) || defined(STM32F427_437xx)

+#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \

+    defined(__DOXYGEN__)

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

 #define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

@@ -348,746 +326,8 @@
 #define STM32_HAS_CRC                       TRUE

 #define STM32_CRC_PROGRAMMABLE              FALSE

 

-#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */

-

-/*===========================================================================*/

-/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F2XX.            */

-/*===========================================================================*/

-#if defined(STM32F40_41xxx) || defined(STM32F2XX)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      TRUE

-#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN                  0x00001100

-

-#define STM32_HAS_ADC3                      TRUE

-#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1))

-#define STM32_ADC3_DMA_CHN                  0x00000022

-

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      TRUE

-#define STM32_HAS_CAN2                      TRUE

-#define STM32_CAN_MAX_FILTERS               28

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  TRUE

-#define STM32_DAC1_CH1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_DAC1_CH1_DMA_CHN              0x00700000

-

-#define STM32_HAS_DAC1_CH2                  TRUE

-#define STM32_DAC1_CH2_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_DAC1_CH2_DMA_CHN              0x07000000

-

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#if defined(STM32F405xx) || defined(STM32F415xx)

-#define STM32_HAS_ETH                       FALSE

-#else

-#define STM32_HAS_ETH                       TRUE

-#endif

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     TRUE

-#define STM32_HAS_GPIOG                     TRUE

-#define STM32_HAS_GPIOI                     TRUE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN |          \

-                                             RCC_AHB1ENR_GPIOFEN |          \

-                                             RCC_AHB1ENR_GPIOGEN |          \

-                                             RCC_AHB1ENR_GPIOHEN |          \

-                                             RCC_AHB1ENR_GPIOIEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#if !defined(STM32F2XX)

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#else

-#define STM32_RTC_HAS_SUBSECONDS            FALSE

-#endif

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

+#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */

 

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      FALSE

-#define STM32_HAS_SPI5                      FALSE

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM6                      TRUE

-#define STM32_TIM6_IS_32BITS                FALSE

-#define STM32_TIM6_CHANNELS                 0

-

-#define STM32_HAS_TIM7                      TRUE

-#define STM32_TIM7_IS_32BITS                FALSE

-#define STM32_TIM7_CHANNELS                 0

-

-#define STM32_HAS_TIM8                      TRUE

-#define STM32_TIM8_IS_32BITS                FALSE

-#define STM32_TIM8_CHANNELS                 6

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM12                     TRUE

-#define STM32_TIM12_IS_32BITS               FALSE

-#define STM32_TIM12_CHANNELS                2

-

-#define STM32_HAS_TIM13                     TRUE

-#define STM32_TIM13_IS_32BITS               FALSE

-#define STM32_TIM13_CHANNELS                2

-

-#define STM32_HAS_TIM14                     TRUE

-#define STM32_TIM14_IS_32BITS               FALSE

-#define STM32_TIM14_CHANNELS                2

-

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    TRUE

-#define STM32_USART3_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 1)

-#define STM32_USART3_RX_DMA_CHN             0x00000040

-#define STM32_USART3_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_USART3_TX_DMA_CHN             0x00074000

-

-#define STM32_HAS_UART4                     TRUE

-#define STM32_UART4_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_UART4_RX_DMA_CHN              0x00000400

-#define STM32_UART4_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_UART4_TX_DMA_CHN              0x00040000

-

-#define STM32_HAS_UART5                     TRUE

-#define STM32_UART5_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)

-#define STM32_UART5_RX_DMA_CHN              0x00000004

-#define STM32_UART5_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_UART5_TX_DMA_CHN              0x40000000

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      TRUE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      TRUE

-#define STM32_FSMC_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_FSMC_DMA_CHN                  0x03010201

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */

-

-/*===========================================================================*/

-/* STM32F401xx.                                                              */

-/*===========================================================================*/

-#if defined(STM32F401xx)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      TRUE

-#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN                  0x00001100

-

-#define STM32_HAS_ADC3                      TRUE

-#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 1))

-#define STM32_ADC3_DMA_CHN                  0x00000022

-

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      TRUE

-#define STM32_HAS_CAN2                      TRUE

-#define STM32_CAN_MAX_FILTERS               28

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  FALSE

-#define STM32_HAS_DAC1_CH2                  FALSE

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH                       FALSE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     FALSE

-#define STM32_HAS_GPIOG                     FALSE

-#define STM32_HAS_GPIOI                     FALSE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      TRUE

-#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_SPI4_RX_DMA_CHN               0x00005004

-#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_SPI4_TX_DMA_CHN               0x00050040

-

-#define STM32_HAS_SPI5                      FALSE

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM6                      FALSE

-#define STM32_HAS_TIM7                      FALSE

-#define STM32_HAS_TIM8                      FALSE

-#define STM32_HAS_TIM12                     FALSE

-#define STM32_HAS_TIM13                     FALSE

-#define STM32_HAS_TIM14                     FALSE

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    FALSE

-#define STM32_HAS_UART4                     FALSE

-#define STM32_HAS_UART5                     FALSE

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      FALSE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      FALSE

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif /* defined(STM32F401xx) */

-

-/*===========================================================================*/

-/* STM32F411xE.                                                              */

-/*===========================================================================*/

-#if defined(STM32F411xx)

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN                  0x00000000

-

-#define STM32_HAS_ADC2                      FALSE

-#define STM32_HAS_ADC3                      FALSE

-#define STM32_HAS_ADC4                      FALSE

-

-#define STM32_HAS_SDADC1                    FALSE

-#define STM32_HAS_SDADC2                    FALSE

-#define STM32_HAS_SDADC3                    FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      FALSE

-#define STM32_HAS_CAN2                      FALSE

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  FALSE

-#define STM32_HAS_DAC1_CH2                  FALSE

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH                       FALSE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS             23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA                     TRUE

-#define STM32_HAS_GPIOB                     TRUE

-#define STM32_HAS_GPIOC                     TRUE

-#define STM32_HAS_GPIOD                     TRUE

-#define STM32_HAS_GPIOE                     TRUE

-#define STM32_HAS_GPIOH                     TRUE

-#define STM32_HAS_GPIOF                     FALSE

-#define STM32_HAS_GPIOG                     FALSE

-#define STM32_HAS_GPIOI                     FALSE

-#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

-                                             RCC_AHB1ENR_GPIOBEN |          \

-                                             RCC_AHB1ENR_GPIOCEN |          \

-                                             RCC_AHB1ENR_GPIODEN |          \

-                                             RCC_AHB1ENR_GPIOEEN |          \

-                                             RCC_AHB1ENR_GPIOHEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN               0x00100001

-#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN               0x11000000

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN               0x00007700

-#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

-#define STM32_I2C2_TX_DMA_CHN               0x70000000

-

-#define STM32_HAS_I2C3                      TRUE

-#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_I2C3_RX_DMA_CHN               0x00000300

-#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_I2C3_TX_DMA_CHN               0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN              0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN               0x00000303

-#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN               0x00303000

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI2_RX_DMA_CHN               0x00000000

-#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI3                      TRUE

-#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN               0x00000000

-#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

-                                             STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN               0x00000000

-

-#define STM32_HAS_SPI4                      TRUE

-#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_SPI4_RX_DMA_CHN               0x00005004

-#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_SPI4_TX_DMA_CHN               0x00050040

-

-#define STM32_HAS_SPI5                      TRUE

-#define STM32_SPI5_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI5_RX_DMA_CHN               0x00702000

-#define STM32_SPI5_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 4) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SPI5_TX_DMA_CHN               0x07020000

-

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM1                      TRUE

-#define STM32_TIM1_IS_32BITS                FALSE

-#define STM32_TIM1_CHANNELS                 4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM5                      TRUE

-#define STM32_TIM5_IS_32BITS                TRUE

-#define STM32_TIM5_CHANNELS                 4

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM6                      FALSE

-#define STM32_HAS_TIM7                      FALSE

-#define STM32_HAS_TIM8                      FALSE

-#define STM32_HAS_TIM12                     FALSE

-#define STM32_HAS_TIM13                     FALSE

-#define STM32_HAS_TIM14                     FALSE

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN             0x00400400

-#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

-#define STM32_USART1_TX_DMA_CHN             0x40000000

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_USART2_RX_DMA_CHN             0x00400000

-#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

-#define STM32_USART2_TX_DMA_CHN             0x04000000

-

-#define STM32_HAS_USART3                    FALSE

-#define STM32_HAS_UART4                     FALSE

-#define STM32_HAS_UART5                     FALSE

-

-#define STM32_HAS_USART6                    TRUE

-#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN             0x00000550

-#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

-                                             STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN             0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       FALSE

-#define STM32_HAS_OTG1                      TRUE

-#define STM32_HAS_OTG2                      FALSE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      FALSE

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#endif

 /** @} */

 

 #endif /* _STM32_REGISTRY_H_ */