diff options
| author | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-13 18:40:44 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-13 18:40:44 +0000 |
| commit | 062b4f7d37eab6c2deea02732e19eb641764a31e (patch) | |
| tree | 4a3ee3e521b4fc5282e550643304d1f12dae1744 /os/hal/ports | |
| parent | feb109f031da25adb5276fbe68eff58883e01d22 (diff) | |
| download | ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.tar.gz ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.tar.bz2 ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.zip | |
Fixed bugs #980 and #981.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12357 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 23 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 25 |
3 files changed, 35 insertions, 15 deletions
diff --git a/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt b/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt index f2abe5efc..ed215722f 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt +++ b/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt @@ -9,6 +9,6 @@ F3xx 1 2 3 * * * * * * * * * * F37x * * * * * * * * * * * * * *
F4xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6
F7xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6 *
-L0xx * * * * *
+L0xx * * * * * * *
L1xx * * * * * * * * *
L4xx 1 2 3 * * * * * * * * * * * 1 2 3 * *
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 510ecb6dc..b8f2b6d7e 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -489,6 +489,29 @@ #define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
* @brief Enables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 1a0381bf5..f3ea21b41 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -34,7 +34,7 @@ * @{
*/
/*===========================================================================*/
-/* STM32L011xx */
+/* STM32L011xx. */
/*===========================================================================*/
#if defined(STM32L011xx) || defined(__DOXYGEN__)
@@ -252,9 +252,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
-/* STM32L031xx */
+/* STM32L031xx. */
/*===========================================================================*/
-#elif defined(STM32L031xx) || defined(__DOXYGEN__)
+#elif defined(STM32L031xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
@@ -473,10 +473,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
-/* STM32L051xx, STM32L061xx */
+/* STM32L051xx, STM32L061xx. */
/*===========================================================================*/
-#elif defined(STM32L051xx) || defined(STM32L061xx) || \
- defined(__DOXYGEN__)
+#elif defined(STM32L051xx) || defined(STM32L061xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
@@ -728,8 +727,7 @@ /*===========================================================================*/
/* STM32L052xx, STM32L062xx. */
/*===========================================================================*/
-#elif defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(__DOXYGEN__)
+#elif defined(STM32L052xx) || defined(STM32L062xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
@@ -988,8 +986,7 @@ /*===========================================================================*/
/* STM32L053xx, STM32L063xx. */
/*===========================================================================*/
-#elif defined(STM32L053xx) || defined(STM32L063xx) || \
- defined(__DOXYGEN__)
+#elif defined(STM32L053xx) || defined(STM32L063xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
@@ -1246,9 +1243,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
-/* STM32L071xx */
+/* STM32L071xx. */
/*===========================================================================*/
-#elif defined(STM32L071xx) || defined(__DOXYGEN__)
+#elif defined(STM32L071xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
@@ -1543,9 +1540,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/
-/* STM32L072xx/STM32L073xx */
+/* STM32L072xx, STM32L073xx. */
/*===========================================================================*/
-#elif defined(STM32L072xx) || defined(STM32L073xx) || defined(__DOXYGEN__)
+#elif defined(STM32L072xx) || defined(STM32L073xx)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
|