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| author | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-13 18:40:44 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-13 18:40:44 +0000 |
| commit | 062b4f7d37eab6c2deea02732e19eb641764a31e (patch) | |
| tree | 4a3ee3e521b4fc5282e550643304d1f12dae1744 /os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | |
| parent | feb109f031da25adb5276fbe68eff58883e01d22 (diff) | |
| download | ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.tar.gz ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.tar.bz2 ChibiOS-062b4f7d37eab6c2deea02732e19eb641764a31e.zip | |
Fixed bugs #980 and #981.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12357 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 510ecb6dc..b8f2b6d7e 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -489,6 +489,29 @@ #define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
* @brief Enables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
|