diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 10:00:10 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 10:00:10 +0000 |
| commit | c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e (patch) | |
| tree | 2a311a668f5a0949effc3146322d3d2961707c44 /os/hal/ports/STM32/STM32F0xx | |
| parent | a8c5d48bcfbc6f3cd7284638d30af7c8f4400341 (diff) | |
| download | ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.tar.gz ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.tar.bz2 ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.zip | |
Experimental support for STM32F09x devices, not tested yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8375 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.c | 119 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_isr.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 461 |
4 files changed, 581 insertions, 9 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index 2250a031a..21bec48ba 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -93,6 +93,125 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH23_HANDLER) */
+
+#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5.*/
+ dmaServeInterrupt(DMA1, 5);
+
+#if STM32_DMA1_NUM_CHANNELS > 5
+ /* Check on channel 6.*/
+ dmaServeInterrupt(DMA1, 6);
+#endif
+
+#if STM32_DMA1_NUM_CHANNELS > 6
+ /* Check on channel 7.*/
+ dmaServeInterrupt(DMA1, 7);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
+
+#if defined(STM32_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2 of DMA1.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3 of DMA1.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ /* Check on channel 1 of DMA2.*/
+ dmaServeInterrupt(DMA2, 1);
+
+ /* Check on channel 2 of DMA2.*/
+ dmaServeInterrupt(DMA2, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH23_CH12_HANDLER) */
+
+#if defined(STM32_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA1.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5 of DMA1.*/
+ dmaServeInterrupt(DMA1, 5);
+
+ /* Check on channel 6 of DMA1.*/
+ dmaServeInterrupt(DMA1, 6);
+
+ /* Check on channel 7 of DMA1.*/
+ dmaServeInterrupt(DMA1, 7);
+
+ /* Check on channel 3 of DMA2.*/
+ dmaServeInterrupt(DMA2, 3);
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(DMA2, 4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(DMA2, 5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH4567_CH345_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index 6255ddcc8..c6f93a541 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -96,6 +96,12 @@ #elif defined(STM32F070xB)
#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
+#elif defined(STM32F091x8)
+#define PLATFORM_NAME "STM32F091x8 Entry Level Medium Density devices"
+
+#elif defined(STM32F098xx)
+#define PLATFORM_NAME "STM32F098xx Entry Level Medium Density devices"
+
#else
#error "STM32F0xx device not specified"
#endif
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h index f86cb20aa..7cd057f8c 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h @@ -66,11 +66,11 @@ */
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
-#define STM32_USART3456_HANDLER VectorB4
+#define STM32_USART3_8_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
-#define STM32_USART3456_NUMBER 29
+#define STM32_USART3_8_NUMBER 29
/*
* USB units.
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 9c76d2781..c1fba4bbb 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -75,6 +75,8 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -82,7 +84,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -290,6 +304,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -297,7 +312,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -516,6 +543,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -523,7 +551,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -709,6 +749,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -716,7 +757,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -890,6 +943,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -897,7 +951,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1086,6 +1152,7 @@ #define STM32_DMA_SUPPORTS_CSELR FALSE
#endif
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -1093,7 +1160,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1344,6 +1423,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -1351,7 +1431,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1532,6 +1624,361 @@ #define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE FALSE
+/*===========================================================================*/
+/* STM32F091x8, STM32F098xx. */
+/*===========================================================================*/
+#elif defined(STM32F091x8) || defined(STM32F098xx)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(3, 5))
+#define STM32_ADC1_DMA_CHN 0x00100011
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+#define STM32_HAS_CAN2 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000100
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH2_DMA_CHN 0x00001000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 5
+
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA12_CH23_CH12_HANDLER Vector68
+#define STM32_DMA12_CH4567_CH345_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA12_CH23_CH12_NUMBER 10
+#define STM32_DMA12_CH4567_CH345_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH1_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define DMA1_CH2_CMASK 0x00000186U
+#define DMA1_CH3_CMASK 0x00000186U
+#define DMA2_CH1_CMASK 0x00000186U
+#define DMA2_CH2_CMASK 0x00000186U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH3_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define DMA1_CH4_CMASK 0x00000E78U
+#define DMA1_CH5_CMASK 0x00000E78U
+#define DMA1_CH6_CMASK 0x00000E78U
+#define DMA1_CH7_CMASK 0x00000E78U
+#define DMA2_CH3_CMASK 0x00000E78U
+#define DMA2_CH4_CMASK 0x00000E78U
+#define DMA2_CH5_CMASK 0x00000E78U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7F840000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x02000200
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00200002
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000330
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00003300
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00303000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x03030000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART1_RX_DMA_CHN 0x00880888
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_TX_DMA_CHN 0x08088088
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART2_RX_DMA_CHN 0x00990999
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART2_TX_DMA_CHN 0x09099099
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART3_RX_DMA_CHN 0x00AA0AAA
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART3_TX_DMA_CHN 0x0A0AA0AA
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART4_RX_DMA_CHN 0x00BB0BBB
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x0B0BB0BB
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART5_RX_DMA_CHN 0x00CC0CCC
+#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART5_TX_DMA_CHN 0x0C0CC0CC
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART6_RX_DMA_CHN 0x00DD0DDD
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART6_TX_DMA_CHN 0x0D0DD0DD
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART7_RX_DMA_CHN 0x00EE0EEE
+#define STM32_UART7_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART7_TX_DMA_CHN 0x0E0EE0EE
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART8_RX_DMA_CHN 0x00FF0FFF
+#define STM32_UART8_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART8_TX_DMA_CHN 0x0F0FF0FF
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
#else
#error "STM32F0xx device not specified"
#endif
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