diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 10:00:10 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 10:00:10 +0000 |
| commit | c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e (patch) | |
| tree | 2a311a668f5a0949effc3146322d3d2961707c44 /os/hal | |
| parent | a8c5d48bcfbc6f3cd7284638d30af7c8f4400341 (diff) | |
| download | ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.tar.gz ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.tar.bz2 ChibiOS-c499423d9c87fe2ef3c5b9a0cd11aeb871a9701e.zip | |
Experimental support for STM32F09x devices, not tested yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8375 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/notes.txt | 18 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 348 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h | 32 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv2/serial_lld.c | 22 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv2/serial_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.c | 119 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_isr.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 461 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/hal_lld.c | 22 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/stm32_registry.h | 5 |
11 files changed, 778 insertions, 265 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv1/notes.txt b/os/hal/ports/STM32/LLD/DMAv1/notes.txt index 4838fa8d4..1b684aa2c 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/notes.txt +++ b/os/hal/ports/STM32/LLD/DMAv1/notes.txt @@ -3,7 +3,7 @@ STM32 DMAv1 driver. Driver capability:
- The driver supports the STM32 traditional DMA controller in the following
- configurations: 5ch, 7ch, 7ch+5ch.
+ configurations: 5ch, 7ch, 7ch+5ch, 7ch+7ch.
- Support for automatic the channel selection through the CSELR register.
- For devices without CSELR register it is possible to select channels but
the SYSCFG CFGR register is not configured, the user has to configure it
@@ -19,15 +19,7 @@ STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other channels. Probably will be removed in the
future.
STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
-STM32_DMAn_NUM_CHANNELS - Number of channels in DMA "n".
-STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x".
-STM32_DMAn_CHxyz_HANDLER - Vector name for shared IRQs "x", "y" and "z".
-STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x".
-STM32_DMAn_CHxyz_NUMBER - Vector number for shared IRQs "x", "y" and "z".
-
-Currently supported shared combinations are:
-
-STM32_DMA1_CH23_HANDLER
-STM32_DMA1_CH23_NUMBER
-STM32_DMA1_CH4567_HANDLER
-STM32_DMA1_CH4567_NUMBER
+STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2).
+STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro
+ is not exported then the ISR is not declared.
+STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7).
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index c4a3c8cd2..901d30d1d 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -55,26 +55,6 @@ */
#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
-/*
- * Handling devices with shared DMA IRQ handlers.
- */
-#if defined(STM32_DMA1_CH23_NUMBER)
-#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
-#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
-#endif
-
-#if defined(STM32_DMA1_CH4567_NUMBER)
-#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
-#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
-#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
-#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
-#endif
-
-#if defined(STM32_DMA2_CH45_NUMBER)
-#define STM32_DMA2_CH4_NUMBER STM32_DMA2_CH45_NUMBER
-#define STM32_DMA2_CH5_NUMBER STM32_DMA2_CH45_NUMBER
-#endif
-
#if STM32_DMA_SUPPORTS_CSELR == TRUE
#define ADDR_DMA1_CSELR &DMA1_CSELR->CSELR
#define ADDR_DMA2_CSELR &DMA2_CSELR->CSELR
@@ -84,36 +64,54 @@ #endif
/*
- * ISR collision masks.
+ * Default ISR collision masks.
*/
+#if !defined(DMA1_CH1_CMASK)
#define DMA1_CH1_CMASK 0x00000001U
-#if !defined(STM32_DMA1_CH23_NUMBER)
+#endif
+
+#if !defined(DMA1_CH2_CMASK)
#define DMA1_CH2_CMASK 0x00000002U
+#endif
+
+#if !defined(DMA1_CH3_CMASK)
#define DMA1_CH3_CMASK 0x00000004U
-#else
-#define DMA1_CH2_CMASK 0x00000006U
-#define DMA1_CH3_CMASK 0x00000006U
#endif
-#if !defined(STM32_DMA1_CH4567_NUMBER)
+
+#if !defined(DMA1_CH4_CMASK)
#define DMA1_CH4_CMASK 0x00000008U
+#endif
+
+#if !defined(DMA1_CH5_CMASK)
#define DMA1_CH5_CMASK 0x00000010U
+#endif
+
+#if !defined(DMA1_CH6_CMASK)
#define DMA1_CH6_CMASK 0x00000020U
+#endif
+
+#if !defined(DMA1_CH7_CMASK)
#define DMA1_CH7_CMASK 0x00000040U
-#else
-#define DMA1_CH4_CMASK 0x00000078U
-#define DMA1_CH5_CMASK 0x00000078U
-#define DMA1_CH6_CMASK 0x00000078U
-#define DMA1_CH7_CMASK 0x00000078U
#endif
+
+#if !defined(DMA2_CH1_CMASK)
#define DMA2_CH1_CMASK 0x00000080U
+#endif
+
+#if !defined(DMA2_CH2_CMASK)
#define DMA2_CH2_CMASK 0x00000100U
+#endif
+
+#if !defined(DMA2_CH3_CMASK)
#define DMA2_CH3_CMASK 0x00000200U
-#if !defined(STM32_DMA2_CH45_NUMBER)
+#endif
+
+#if !defined(DMA2_CH4_CMASK)
#define DMA2_CH4_CMASK 0x00000400U
+#endif
+
+#if !defined(DMA2_CH5_CMASK)
#define DMA2_CH5_CMASK 0x00000800U
-#else
-#define DMA2_CH4_CMASK 0x00000C00U
-#define DMA2_CH5_CMASK 0x00000C00U
#endif
/*===========================================================================*/
@@ -143,33 +141,31 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { {DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
{DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
{DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
+#if STM32_DMA2_NUM_CHANNELS > 5
+ {DMA2_Channel6, DMA2_CH6_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},
+#if STM32_DMA2_NUM_CHANNELS > 6
+ {DMA2_Channel6, DMA2_CH7_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},
+#endif
+#endif
#endif
#endif
#endif
};
+/**
+ * @brief DMA IRQ redirectors.
+ */
+dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS];
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
- void *dma_param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
* @brief Mask of the allocated streams.
*/
static uint32_t dma_streams_mask;
-/**
- * @brief DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -178,337 +174,229 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; /* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 1 shared interrupt handler.
+ * @brief DMA1 stream 1 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 0;
- if (dma_isr_redir[0].dma_func)
- dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+ dmaServeInterrupt(DMA1, 1);
OSAL_IRQ_EPILOGUE();
}
+#endif
-/* Channels 2 and 3 are shared on some devices.*/
-#if defined(STM32_DMA1_CH23_HANDLER)
-/**
- * @brief DMA1 streams 2 and 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- /* Check on channel 2.*/
- flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 4;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
- }
-
- /* Check on channel 3.*/
- flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 8;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#else /*!defined(STM32_DMA1_CH23_HANDLER) */
+#if defined(STM32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 2 shared interrupt handler.
+ * @brief DMA1 stream 2 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 4;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+ dmaServeInterrupt(DMA1, 2);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if defined(STM32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 3 shared interrupt handler.
+ * @brief DMA1 stream 3 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 8;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+ dmaServeInterrupt(DMA1, 3);
OSAL_IRQ_EPILOGUE();
}
-#endif /*!defined(STM32_DMA1_CH23_HANDLER) */
-
-/* Channels 4, 5, 6 and 7 are shared on some devices.*/
-#if defined(STM32_DMA1_CH4567_HANDLER)
-/**
- * @brief DMA1 streams 4 and 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- /* Check on channel 4.*/
- flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 12;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
- }
-
- /* Check on channel 5.*/
- flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 16;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
- }
-
-#if STM32_DMA1_NUM_CHANNELS > 5
- /* Check on channel 6.*/
- flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 20;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
- }
-#endif
-
-#if STM32_DMA1_NUM_CHANNELS > 6
- /* Check on channel 7.*/
- flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
- if (flags & STM32_DMA_ISR_MASK) {
- DMA1->IFCR = flags << 24;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
- }
#endif
- OSAL_IRQ_EPILOGUE();
-}
-#else /* !defined(STM32_DMA1_CH4567_HANDLER) */
+#if defined(STM32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 4 shared interrupt handler.
+ * @brief DMA1 stream 4 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 12;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+ dmaServeInterrupt(DMA1, 4);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if defined(STM32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 5 shared interrupt handler.
+ * @brief DMA1 stream 5 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 16;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+ dmaServeInterrupt(DMA1, 5);
OSAL_IRQ_EPILOGUE();
}
+#endif
-#if (STM32_DMA1_NUM_CHANNELS > 5) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 6 shared interrupt handler.
+ * @brief DMA1 stream 6 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 20;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+ dmaServeInterrupt(DMA1, 6);
OSAL_IRQ_EPILOGUE();
}
-#endif /* STM32_DMA1_NUM_CHANNELS > 5 */
+#endif
-#if (STM32_DMA1_NUM_CHANNELS > 6) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA1 stream 7 shared interrupt handler.
+ * @brief DMA1 stream 7 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
- DMA1->IFCR = flags << 24;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+ dmaServeInterrupt(DMA1, 7);
OSAL_IRQ_EPILOGUE();
}
-#endif /* STM32_DMA1_NUM_CHANNELS > 6 */
-#endif /* !defined(STM32_DMA1_CH4567_HANDLER) */
+#endif
-#if (STM32_DMA2_NUM_CHANNELS > 0) || defined(__DOXYGEN__)
+#if defined(STM32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 stream 1 shared interrupt handler.
+ * @brief DMA2 stream 1 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 0;
- if (dma_isr_redir[7].dma_func)
- dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+ dmaServeInterrupt(DMA2, 1);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if defined(STM32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 stream 2 shared interrupt handler.
+ * @brief DMA2 stream 2 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 4;
- if (dma_isr_redir[8].dma_func)
- dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+ dmaServeInterrupt(DMA2, 2);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if defined(STM32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 stream 3 shared interrupt handler.
+ * @brief DMA2 stream 3 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 8;
- if (dma_isr_redir[9].dma_func)
- dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+ dmaServeInterrupt(DMA2, 3);
OSAL_IRQ_EPILOGUE();
}
+#endif
-/* Channels 4 and 5 are shared on some devices.*/
-#if defined(STM32_DMA2_CH45_HANDLER)
+#if defined(STM32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 streams 4 and 5 shared interrupt handler.
+ * @brief DMA2 stream 4 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
- uint32_t flags;
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 12;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+ dmaServeInterrupt(DMA2, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(STM32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 stream 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 16;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+ dmaServeInterrupt(DMA2, 5);
OSAL_IRQ_EPILOGUE();
}
-#else /* !defined(STM32_DMA2_CH45_HANDLER) */
+#endif
+
+#if defined(STM32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 stream 4 shared interrupt handler.
+ * @brief DMA2 stream 6 shared ISR.
*
* @isr
*/
-OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
- uint32_t flags;
+OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 12;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+ dmaServeInterrupt(DMA2, 6);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if defined(STM32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__)
/**
- * @brief DMA2 stream 5 shared interrupt handler.
+ * @brief DMA2 stream 7 shared ISR.
*
* @isr
*/
-OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
- uint32_t flags;
+OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
OSAL_IRQ_PROLOGUE();
- flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->IFCR = flags << 16;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+ dmaServeInterrupt(DMA2, 7);
OSAL_IRQ_EPILOGUE();
}
-#endif /* defined(STM32_DMA2_CH45_HANDLER) */
-#endif /* STM32_DMA2_NUM_CHANNELS > 0 */
+#endif
/*===========================================================================*/
/* Driver exported functions. */
@@ -525,7 +413,7 @@ void dmaInit(void) { dma_streams_mask = 0U;
for (i = 0; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].channel->CCR = 0U;
- dma_isr_redir[i].dma_func = NULL;
+ _stm32_dma_isr_redir[i].dma_func = NULL;
}
DMA1->IFCR = 0xFFFFFFFFU;
#if STM32_DMA2_NUM_CHANNELS > 0
@@ -569,8 +457,8 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, return true;
/* Installs the DMA handler.*/
- dma_isr_redir[dmastp->selfindex].dma_func = func;
- dma_isr_redir[dmastp->selfindex].dma_param = param;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_func = func;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_param = param;
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
@@ -629,8 +517,8 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { }
/* Removes the DMA handler.*/
- dma_isr_redir[dmastp->selfindex].dma_func = NULL;
- dma_isr_redir[dmastp->selfindex].dma_param = NULL;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_func = NULL;
+ _stm32_dma_isr_redir[dmastp->selfindex].dma_param = NULL;
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h index c8ccbfc84..157e9432d 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h @@ -44,6 +44,11 @@ #define STM32_DMA_ISR_MASK 0x0F
/**
+ * @brief From stream number to shift factor in @p ISR and @p IFCR registers.
+ */
+#define STM32_DMA_ISR_SHIFT(stream) (((stream) - 1U) * 4U)
+
+/**
* @brief Returns the request line associated to the specified stream.
* @note In some STM32 manuals the request line is named confusingly
* channel.
@@ -232,6 +237,14 @@ typedef struct { */
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+/**
+ * @brief DMA ISR redirector type.
+ */
+typedef struct {
+ stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
+ void *dma_param; /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -412,6 +425,24 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); dmaStreamDisable(dmastp); \
}
+/**
+ * @brief Serves a DMA IRQ.
+ *
+ * @param[in] dma pointer to the DMA block
+ * @param[in] s stream to serve
+ */
+#define dmaServeInterrupt(dma, s) { \
+ uint32_t flags; \
+ \
+ flags = ((dma)->ISR >> STM32_DMA_ISR_SHIFT(s)) & STM32_DMA_ISR_MASK; \
+ if (flags & STM32_DMA_ISR_MASK) { \
+ (dma)->IFCR = flags << STM32_DMA_ISR_SHIFT(s); \
+ if (_stm32_dma_isr_redir[s].dma_func) { \
+ _stm32_dma_isr_redir[s].dma_func(_stm32_dma_isr_redir[s].dma_param, \
+ flags); \
+ } \
+ } \
+}
/** @} */
/*===========================================================================*/
@@ -420,6 +451,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+extern dma_isr_redir_t _stm32_dma_isr_redir[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
diff --git a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c index 1d030621e..683df0481 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c @@ -334,15 +334,16 @@ OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) { }
#endif
-#if defined(STM32_USART3456_HANDLER)
-#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
- STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+#if defined(STM32_USART3_8_HANDLER)
+#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
+ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \
+ STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
/**
* @brief USART2 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(STM32_USART3456_HANDLER) {
+OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
OSAL_IRQ_PROLOGUE();
@@ -363,7 +364,7 @@ OSAL_IRQ_HANDLER(STM32_USART3456_HANDLER) { }
#endif
-#else /* !defined(STM32_USART3456_HANDLER) */
+#else /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if !defined(STM32_USART3_HANDLER)
@@ -441,7 +442,7 @@ OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) { }
#endif
-#endif /* !defined(STM32_USART3456_HANDLER) */
+#endif /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if !defined(STM32_UART7_HANDLER)
@@ -564,10 +565,11 @@ void sd_lld_init(void) { #endif
#endif
-#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
- STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-#if defined(STM32_USART3456_HANDLER)
- nvicEnableVector(STM32_USART3456_NUMBER, STM32_SERIAL_USART3456_PRIORITY);
+#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
+ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \
+ STM32_SERIAL_USE_UART7 || STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
+#if defined(STM32_USART3_8_HANDLER)
+ nvicEnableVector(STM32_USART3_8_NUMBER, STM32_SERIAL_USART3_8_PRIORITY);
#endif
#endif
}
diff --git a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h index 5989e560b..ba3d9ed94 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h @@ -133,11 +133,11 @@ #endif
/**
- * @brief USART3, 4, 5 and 6 interrupt priority level setting.
+ * @brief USART3..8 interrupt priority level setting.
* @note Only valid on those devices with a shared IRQ.
*/
-#if !defined(STM32_SERIAL_USART3456_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART3456_PRIORITY 12
+#if !defined(STM32_SERIAL_USART3_8_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_8_PRIORITY 12
#endif
/**
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index 2250a031a..21bec48ba 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -93,6 +93,125 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH23_HANDLER) */
+
+#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5.*/
+ dmaServeInterrupt(DMA1, 5);
+
+#if STM32_DMA1_NUM_CHANNELS > 5
+ /* Check on channel 6.*/
+ dmaServeInterrupt(DMA1, 6);
+#endif
+
+#if STM32_DMA1_NUM_CHANNELS > 6
+ /* Check on channel 7.*/
+ dmaServeInterrupt(DMA1, 7);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
+
+#if defined(STM32_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2 of DMA1.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3 of DMA1.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ /* Check on channel 1 of DMA2.*/
+ dmaServeInterrupt(DMA2, 1);
+
+ /* Check on channel 2 of DMA2.*/
+ dmaServeInterrupt(DMA2, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH23_CH12_HANDLER) */
+
+#if defined(STM32_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA1.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5 of DMA1.*/
+ dmaServeInterrupt(DMA1, 5);
+
+ /* Check on channel 6 of DMA1.*/
+ dmaServeInterrupt(DMA1, 6);
+
+ /* Check on channel 7 of DMA1.*/
+ dmaServeInterrupt(DMA1, 7);
+
+ /* Check on channel 3 of DMA2.*/
+ dmaServeInterrupt(DMA2, 3);
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(DMA2, 4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(DMA2, 5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH4567_CH345_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index 6255ddcc8..c6f93a541 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -96,6 +96,12 @@ #elif defined(STM32F070xB)
#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
+#elif defined(STM32F091x8)
+#define PLATFORM_NAME "STM32F091x8 Entry Level Medium Density devices"
+
+#elif defined(STM32F098xx)
+#define PLATFORM_NAME "STM32F098xx Entry Level Medium Density devices"
+
#else
#error "STM32F0xx device not specified"
#endif
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h index f86cb20aa..7cd057f8c 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h @@ -66,11 +66,11 @@ */
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
-#define STM32_USART3456_HANDLER VectorB4
+#define STM32_USART3_8_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
-#define STM32_USART3456_NUMBER 29
+#define STM32_USART3_8_NUMBER 29
/*
* USB units.
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 9c76d2781..c1fba4bbb 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -75,6 +75,8 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
+
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -82,7 +84,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -290,6 +304,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -297,7 +312,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -516,6 +543,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -523,7 +551,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -709,6 +749,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -716,7 +757,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -890,6 +943,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -897,7 +951,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1086,6 +1152,7 @@ #define STM32_DMA_SUPPORTS_CSELR FALSE
#endif
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -1093,7 +1160,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1344,6 +1423,7 @@ #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 5
+#define STM32_DMA2_NUM_CHANNELS 0
#define STM32_DMA1_CH1_HANDLER Vector64
#define STM32_DMA1_CH23_HANDLER Vector68
#define STM32_DMA1_CH4567_HANDLER Vector6C
@@ -1351,7 +1431,19 @@ #define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH4567_NUMBER 11
-#define STM32_DMA2_NUM_CHANNELS 0
+#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
+#define DMA1_CH2_CMASK 0x00000006U
+#define DMA1_CH3_CMASK 0x00000006U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
+#define DMA1_CH4_CMASK 0x00000078U
+#define DMA1_CH5_CMASK 0x00000078U
+#define DMA1_CH6_CMASK 0x00000078U
+#define DMA1_CH7_CMASK 0x00000078U
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -1532,6 +1624,361 @@ #define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE FALSE
+/*===========================================================================*/
+/* STM32F091x8, STM32F098xx. */
+/*===========================================================================*/
+#elif defined(STM32F091x8) || defined(STM32F098xx)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER FALSE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(3, 5))
+#define STM32_ADC1_DMA_CHN 0x00100011
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+#define STM32_HAS_CAN2 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000100
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH2_DMA_CHN 0x00001000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 5
+
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA12_CH23_CH12_HANDLER Vector68
+#define STM32_DMA12_CH4567_CH345_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA12_CH23_CH12_NUMBER 10
+#define STM32_DMA12_CH4567_CH345_NUMBER 11
+
+#define STM32_DMA1_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA1_CH3_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH1_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define STM32_DMA2_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
+#define DMA1_CH2_CMASK 0x00000186U
+#define DMA1_CH3_CMASK 0x00000186U
+#define DMA2_CH1_CMASK 0x00000186U
+#define DMA2_CH2_CMASK 0x00000186U
+
+#define STM32_DMA1_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH6_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA1_CH7_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH3_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define STM32_DMA2_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
+#define DMA1_CH4_CMASK 0x00000E78U
+#define DMA1_CH5_CMASK 0x00000E78U
+#define DMA1_CH6_CMASK 0x00000E78U
+#define DMA1_CH7_CMASK 0x00000E78U
+#define DMA2_CH3_CMASK 0x00000E78U
+#define DMA2_CH4_CMASK 0x00000E78U
+#define DMA2_CH5_CMASK 0x00000E78U
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 32
+#define STM32_EXTI_IMR_MASK 0x7F840000U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x02000200
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00200002
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000330
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00003300
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00303000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x03030000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART1_RX_DMA_CHN 0x00880888
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_TX_DMA_CHN 0x08088088
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART2_RX_DMA_CHN 0x00990999
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART2_TX_DMA_CHN 0x09099099
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART3_RX_DMA_CHN 0x00AA0AAA
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART3_TX_DMA_CHN 0x0A0AA0AA
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART4_RX_DMA_CHN 0x00BB0BBB
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x0B0BB0BB
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART5_RX_DMA_CHN 0x00CC0CCC
+#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART5_TX_DMA_CHN 0x0C0CC0CC
+
+#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_USART6_RX_DMA_CHN 0x00DD0DDD
+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART6_TX_DMA_CHN 0x0D0DD0DD
+
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART7_RX_DMA_CHN 0x00EE0EEE
+#define STM32_UART7_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART7_TX_DMA_CHN 0x0E0EE0EE
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3)))
+#define STM32_UART8_RX_DMA_CHN 0x00FF0FFF
+#define STM32_UART8_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART8_TX_DMA_CHN 0x0F0FF0FF
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
#else
#error "STM32F0xx device not specified"
#endif
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c index 989ab35a7..7344fb103 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c @@ -92,6 +92,28 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA2_CH45_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA2 streams 4 and 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH45_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(DMA2, 4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(DMA2, 5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA2_CH45_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h index b8fbd815a..4ba797e64 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h @@ -661,6 +661,11 @@ #define STM32_DMA2_CH3_NUMBER 58
#define STM32_DMA2_CH45_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER STM32_DMA2_CH45_NUMBER
+#define STM32_DMA2_CH5_NUMBER STM32_DMA2_CH45_NUMBER
+#define DMA2_CH4_CMASK 0x00000C00U
+#define DMA2_CH5_CMASK 0x00000C00U
+
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
|