diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx/hal_lld.c')
-rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.c | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index 2250a031a..21bec48ba 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -93,6 +93,125 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH23_HANDLER) */
+
+#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5.*/
+ dmaServeInterrupt(DMA1, 5);
+
+#if STM32_DMA1_NUM_CHANNELS > 5
+ /* Check on channel 6.*/
+ dmaServeInterrupt(DMA1, 6);
+#endif
+
+#if STM32_DMA1_NUM_CHANNELS > 6
+ /* Check on channel 7.*/
+ dmaServeInterrupt(DMA1, 7);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
+
+#if defined(STM32_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 2 of DMA1.*/
+ dmaServeInterrupt(DMA1, 2);
+
+ /* Check on channel 3 of DMA1.*/
+ dmaServeInterrupt(DMA1, 3);
+
+ /* Check on channel 1 of DMA2.*/
+ dmaServeInterrupt(DMA2, 1);
+
+ /* Check on channel 2 of DMA2.*/
+ dmaServeInterrupt(DMA2, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH23_CH12_HANDLER) */
+
+#if defined(STM32_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
+ * @note It is declared here because this device has a non-standard
+ * DMA shared IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Check on channel 4 of DMA1.*/
+ dmaServeInterrupt(DMA1, 4);
+
+ /* Check on channel 5 of DMA1.*/
+ dmaServeInterrupt(DMA1, 5);
+
+ /* Check on channel 6 of DMA1.*/
+ dmaServeInterrupt(DMA1, 6);
+
+ /* Check on channel 7 of DMA1.*/
+ dmaServeInterrupt(DMA1, 7);
+
+ /* Check on channel 3 of DMA2.*/
+ dmaServeInterrupt(DMA2, 3);
+
+ /* Check on channel 4 of DMA2.*/
+ dmaServeInterrupt(DMA2, 4);
+
+ /* Check on channel 5 of DMA2.*/
+ dmaServeInterrupt(DMA2, 5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(STM32_DMA12_CH4567_CH345_HANDLER) */
+#endif /* defined(STM32_DMA_REQUIRED) */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
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