Fixed bug #1035.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12854 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

12 files changed, 60 insertions, 13 deletions

diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
index d512e786c..3efb4d819 100644
--- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -60,7 +60,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;

 

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->BDCR = RCC_BDCR_BDRST;

     RCC->BDCR = 0;

@@ -335,6 +335,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
index 5b948be05..577ad9e42 100644
--- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -58,7 +58,7 @@ static void hal_lld_backup_domain_init(void) {
 

 #if HAL_USE_RTC

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->BDCR = RCC_BDCR_BDRST;

     RCC->BDCR = 0;

@@ -316,6 +316,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock.    */

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
index fb398536c..32c953f1f 100644
--- a/os/hal/ports/STM32/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;

 

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->BDCR = RCC_BDCR_BDRST;

     RCC->BDCR = 0;

@@ -199,6 +199,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 766675b65..edb02d9ca 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;

 

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->BDCR = RCC_BDCR_BDRST;

     RCC->BDCR = 0;

@@ -205,6 +205,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 8f3aba7db..96e8056c5 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -184,7 +184,7 @@ void stm32_clock_init(void) {
   /* Registers finally cleared to reset values.*/

   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

   RCC->CFGR = 0;                            /* CFGR reset value.            */

-  

+

 #if STM32_HSE_ENABLED

   /* HSE activation.*/

 #if defined(STM32_HSE_BYPASS)

@@ -314,6 +314,9 @@ void stm32_clock_init(void) {
   FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |

                FLASH_ACR_DCEN | STM32_FLASHBITS;

 #endif

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 53398d411..0014fa578 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -288,6 +288,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup.*/

   FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 

   /* Switching to the configured clock source if it is different from HSI.*/

 #if (STM32_SW != STM32_SW_HSI)

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index df3e2f478..a474eb00e 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -368,6 +368,9 @@ void stm32_clock_init(void) {
 

   /* Flash setup.*/

   FLASH->ACR = FLASH_ACR_WRHIGHFREQ_2 | STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY)) {

+  }

 

   /* Switching to the configured clock source if it is different

      from HSI.*/

diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c
index b9ba22d26..11404bf0f 100644
--- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c
@@ -55,7 +55,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;

 

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->CSR |= RCC_CSR_RTCRST;

     RCC->CSR &= ~RCC_CSR_RTCRST;

@@ -65,7 +65,7 @@ static void hal_lld_backup_domain_init(void) {
 #if STM32_LSE_ENABLED

   RCC->CSR |= RCC_CSR_LSEON;

   while ((RCC->CSR & RCC_CSR_LSERDY) == 0)

-    ;                                     /* Waits until LSE is stable.   */

+    ;                                       /* Waits until LSE is stable.   */

 #endif

 

 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK

@@ -290,6 +290,9 @@ void stm32_clock_init(void) {
   /* Flash setup and final clock selection.*/

 #if defined(STM32_FLASHBITS)

   FLASH->ACR = STM32_FLASHBITS;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+  }

 #endif

 

   /* Switching to the configured clock source if it is different from MSI.  */

diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
index 4ca3335de..cef14c816 100644
--- a/os/hal/ports/STM32/STM32L1xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
@@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;

 

   /* Reset BKP domain if different clock source selected.*/

-  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {

     /* Backup domain reset.*/

     RCC->CSR |= RCC_CSR_RTCRST;

     RCC->CSR &= ~RCC_CSR_RTCRST;

@@ -210,9 +210,15 @@ void stm32_clock_init(void) {
   /* Flash setup and final clock selection.*/

 #if defined(STM32_FLASHBITS1)

   FLASH->ACR = STM32_FLASHBITS1;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS1 & FLASH_ACR_LATENCY_Msk)) {

+  }

 #endif

 #if defined(STM32_FLASHBITS2)

   FLASH->ACR = STM32_FLASHBITS2;

+  while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+         (STM32_FLASHBITS2 & FLASH_ACR_LATENCY_Msk)) {

+  }

 #endif

 

   /* Switching to the configured clock source if it is different from MSI.*/

diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index d62412170..5bc119b1e 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -333,8 +333,12 @@ void stm32_clock_init(void) {
   }

 

   /* Set flash WS's for SYSCLK source */

-  if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)

+  if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {

     FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;

+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+           (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+    }

+  }

 

   /* Switching to the configured SYSCLK source if it is different from MSI.*/

 #if (STM32_SW != STM32_SW_MSI)

@@ -345,8 +349,12 @@ void stm32_clock_init(void) {
 #endif

 

   /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */

-  if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)

+  if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {

     FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;

+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+           (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+    }

+  }

 

 #endif /* STM32_NO_INIT */

 

diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index 216002fc2..7abdd7893 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -18,7 +18,7 @@
  * @file    STM32L4xx/hal_lld.c

  * @brief   STM32L4xx HAL subsystem low level driver source.

  *

- * @addtogroup STM32L4xx_ISR

+ * @addtogroup HAL

  * @{

  */

 

@@ -351,8 +351,12 @@ void stm32_clock_init(void) {
   }

 

   /* Set flash WS's for SYSCLK source */

-  if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)

+  if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {

     FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;

+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+           (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+    }

+  }

 

   /* Switching to the configured SYSCLK source if it is different from MSI.*/

 #if (STM32_SW != STM32_SW_MSI)

@@ -363,8 +367,12 @@ void stm32_clock_init(void) {
 #endif

 

   /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */

-  if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)

+  if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {

     FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;

+    while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=

+           (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {

+    }

+  }

 

 #endif /* STM32_NO_INIT */

 

diff --git a/readme.txt b/readme.txt
index 84428e5cf..0067ea02c 100644
--- a/readme.txt
+++ b/readme.txt
@@ -78,6 +78,7 @@
        generate a library with a pre-configured RT. It also includes

        an "header generator" able to generate an unified "ch.h" with

        all options resolved.

+- FIX: Fixed missing delay after STM32 wait states setup (bug #1035).

 - FIX: Fixed reduced time slices in RT (bug #1034).

 - FIX: Fixed long intervals fail when interval type is larger than time type

        (bug #1031).