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Diffstat (limited to 'os/hal/ports/STM32/STM32L4xx+/hal_lld.c')
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/hal_lld.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index d62412170..5bc119b1e 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -333,8 +333,12 @@ void stm32_clock_init(void) {
}
/* Set flash WS's for SYSCLK source */
- if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)
+ if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
+ }
/* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
@@ -345,8 +349,12 @@ void stm32_clock_init(void) {
#endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
- if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)
+ if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
+ }
#endif /* STM32_NO_INIT */