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Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/hal_lld.c')
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 8f3aba7db..96e8056c5 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -184,7 +184,7 @@ void stm32_clock_init(void) {
/* Registers finally cleared to reset values.*/
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
-
+
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
@@ -314,6 +314,9 @@ void stm32_clock_init(void) {
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#endif
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)