diff options
| -rw-r--r-- | Makefile | 26 | ||||
| -rw-r--r-- | async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl | 7 | ||||
| -rw-r--r-- | sdram_ctrl.vhd | 15 | ||||
| -rw-r--r-- | sdram_test.qsf | 3 | ||||
| -rw-r--r-- | sdram_test.vhd | 82 | ||||
| -rw-r--r-- | sdram_test_mcu.qsys | 156 |
6 files changed, 206 insertions, 83 deletions
@@ -1,6 +1,6 @@ PROJ=sdram_test -SRCS=$(wildcard *.vhd *.v *.qsf *.qpf ) +SRCS=$(wildcard *.vhd *.v *.qsf *.qpf ) ${QSYS}.qsys SRCS += $(shell find async_16bit_bus_adapter_hw -type f -print ) BSP_DIR=bsp @@ -38,7 +38,7 @@ fit.stamp: ans.stamp touch $@ #ans.stamp: source.stamp ${SOPC_FILE} -ans.stamp: source.stamp +ans.stamp: source.stamp tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ} touch $@ @@ -65,17 +65,17 @@ bsp.stamp:${SOPC_FILE} /bin/rm -rf ${BSP_DIR} mkdir -p ${BSP_DIR} tools/wrap nios2-bsp ${BSP_TYPE} ${BSP_DIR} ${SOPC_FILE} ${NIOS2_BSP_ARGS} ${CPU_NAME} -# tools/wrap nios2-bsp-update-settings --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp \ -# --set hal.sys_clk_timer none \ -# --set hal.max_file_descriptors 4 \ -# --set hal.enable_c_plus_plus 0 \ -# --set hal.make.bsp_cflags_optimization -Os \ -# --set hal.enable_exit 0 \ -# --set hal.enable_small_c_library 1 \ -# --set hal.enable_clean_exit 0 \ -# --set hal.enable_reduced_device_drivers 1 \ -# --set hal.enable_lightweight_device_driver_api 1 -# tools/wrap nios2-bsp-generate-files --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp + tools/wrap nios2-bsp-update-settings --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp \ + --set hal.sys_clk_timer none \ + --set hal.max_file_descriptors 4 \ + --set hal.enable_c_plus_plus 0 \ + --set hal.make.bsp_cflags_optimization -Os \ + --set hal.enable_exit 0 \ + --set hal.enable_small_c_library 1 \ + --set hal.enable_clean_exit 0 \ + --set hal.enable_reduced_device_drivers 1 \ + --set hal.enable_lightweight_device_driver_api 1 + tools/wrap nios2-bsp-generate-files --bsp-dir ${BSP_DIR} --settings bsp/settings.bsp tools/wrap make -C ${BSP_DIR} touch $@ diff --git a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl index 08709ff..4223d10 100644 --- a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl +++ b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 20:08:19 BST 2013 +# Mon Oct 14 20:32:15 BST 2013 # DO NOT MODIFY # # async_16bit_bus_adapter "async_16bit_bus_adapter" v1.0 -# 2013.10.14.20:08:19 +# 2013.10.14.20:32:15 # # @@ -85,7 +85,6 @@ set_interface_property avalon_slave burstOnBurstBoundariesOnly false set_interface_property avalon_slave burstcountUnits WORDS set_interface_property avalon_slave explicitAddressSpan 0 set_interface_property avalon_slave holdTime 0 -set_interface_property avalon_slave isMemoryDevice true set_interface_property avalon_slave linewrapBursts false set_interface_property avalon_slave maximumPendingReadTransactions 0 set_interface_property avalon_slave readLatency 0 @@ -106,7 +105,7 @@ add_interface_port avalon_slave rd_n read_n Input 1 add_interface_port avalon_slave wait_n waitrequest_n Output 1 add_interface_port avalon_slave readdata readdata Output 16 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 -set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 1 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd index b0b4a1f..1a54fc3 100644 --- a/sdram_ctrl.vhd +++ b/sdram_ctrl.vhd @@ -17,7 +17,7 @@ entity sdram_ctrl is bus_cs_n : in std_logic; bus_rnw : in std_logic; - bus_wait_n : out std_logic; + bus_done_n : out std_logic; bus_addr : in addr_t; bus_data_in : in data_t; @@ -549,11 +549,12 @@ begin b_state <= B_ST_WAIT_CS_N_LOW; b_debug(6 downto 0) <= DEBUG_0; b_debug(7) <='0'; - bus_wait_n <= '0'; + bus_done_n <= '1'; elsif rising_edge(clock) then if b_state = B_ST_WAIT_CS_N_LOW then b_debug(6 downto 0) <= DEBUG_1; - bus_wait_n <= '0'; + bus_done_n <= '1'; +-- bus_data_out <="1111000111110001"; if l2b_al(bus_cs_n) then -- new request ship it to the main state machine post_request <='1'; @@ -577,6 +578,7 @@ begin -- the logic has pushed the request to the ram if l2b_al(request_rnw) then -- if it's a write we're all done + bus_done_n <='0'; b_state <= B_ST_WAIT_CS_N_HIGH; else -- if it's a read we have to wait for the data @@ -587,14 +589,17 @@ begin b_debug(6 downto 0) <= DEBUG_4; if l2b_ah(r_data_valid(0)) then bus_data_out <= mem_data_in; --- bus_data_out <= request_addr(15 downto 0); + bus_done_n <= '0'; + --bus_data_out <= request_addr(15 downto 0); + --bus_data_out <= bus_addr(15 downto 0); b_state <= B_ST_WAIT_CS_N_HIGH; end if; elsif b_state = B_ST_WAIT_CS_N_HIGH then b_debug(6 downto 0) <= DEBUG_5; b_debug(7) <='1'; - bus_wait_n <= '1'; if not l2b_al(bus_cs_n) then +-- bus_data_out <="1111001011110010"; + bus_done_n <= '1'; b_state <=B_ST_WAIT_CS_N_LOW; end if; else diff --git a/sdram_test.qsf b/sdram_test.qsf index a90ba5d..c0677d9 100644 --- a/sdram_test.qsf +++ b/sdram_test.qsf @@ -151,4 +151,5 @@ set_global_assignment -name VHDL_FILE pllx2.vhd set_global_assignment -name QSYS_FILE sdram_test_mcu.qsys -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/sdram_test.vhd b/sdram_test.vhd index 7fa6729..c916ee2 100644 --- a/sdram_test.vhd +++ b/sdram_test.vhd @@ -46,13 +46,13 @@ component sdram_test_mcu is clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n pio_0_d_export : out std_logic_vector(7 downto 0); -- export - sbb_0_reset_n : out std_logic; -- reset_n - sbb_0_cs_n : out std_logic; -- cs_n - sbb_0_rnw : out std_logic; -- rnw - sbb_0_wait_n : in std_logic := 'X'; -- wait_n - sbb_0_addr : out std_logic_vector(15 downto 0); -- addr - sbb_0_data_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- data_in - sbb_0_data_out : out std_logic_vector(15 downto 0) -- data_out + ebb_0_cs_n : out std_logic; -- cs_n + ebb_0_rnw : out std_logic; -- rnw + ebb_0_done_n : in std_logic := 'X'; -- done_n + ebb_0_addr : out std_logic_vector(15 downto 0); -- addr + ebb_0_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_in + ebb_0_data_out : out std_logic_vector(7 downto 0); -- data_out + ebb_0_reset_n : out std_logic -- reset_n ); end component sdram_test_mcu; @@ -65,7 +65,7 @@ component sdram_ctrl is bus_cs_n : in std_logic; bus_rnw : in std_logic; - bus_wait_n : out std_logic; + bus_done_n : out std_logic; bus_addr : in addr_t; bus_data_in : in data_t; @@ -99,7 +99,7 @@ signal b_data_in : data_t; signal b_data_out : data_t; signal b_cs_n : std_logic; signal b_rnw : std_logic; -signal b_wait_n : std_logic; +signal b_done_n : std_logic; signal pll_reset : std_logic; signal mcu_clock : std_logic; @@ -110,8 +110,8 @@ signal debug : std_logic_vector(7 downto 0); signal global_reset_n : std_logic; signal b_reset_n : std_logic; -signal buf8 : std_logic_vector(7 downto 0); +signal state: std_logic_vector(4 downto 0); begin @@ -127,28 +127,72 @@ begin clk_clk => mcu_clock, -- clk.clk reset_reset_n => global_reset_n, -- reset.reset_n pio_0_d_export => seven_seg, -- pio_0_d.export - sbb_0_reset_n => b_reset_n, - sbb_0_cs_n => b_cs_n, -- ebb_0.cs_n - sbb_0_rnw => b_rnw, -- .rnw - sbb_0_wait_n => b_wait_n, -- .wait_n - sbb_0_addr => b_addr16, -- .addr - sbb_0_data_in => b_data_in, -- .data - sbb_0_data_out => b_data_out -- .data + ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n + ebb_0_rnw => b_rnw, -- .rnw + ebb_0_done_n => b_done_n, -- .done_n + ebb_0_addr => b_addr16, -- .addr + ebb_0_data_in => b_data_in8, -- .data + ebb_0_data_out => b_data_out8, -- .data + ebb_0_reset_n => b_reset_n ); -- bodge buses together +-- +-- fish: process (b_reset_n,b_addr16,b_cs_n,clock_100) begin +-- if l2b_al(b_reset_n) then +-- state <="00001"; +-- b_done_n <= '1'; +-- elsif rising_edge(clock_100) then +-- if state ="00001" then +-- b_done_n <='1'; +-- b_data_in8 <="11110001"; +-- if l2b_al(b_cs_n) then +-- state<="00010"; +-- end if; +-- elsif state="00010" then +-- b_data_in8 <="11110010"; +-- state<="00100"; +-- elsif state="00100" then +-- b_data_in8 <="11110011"; +-- state<="01000"; +-- elsif state="01000" then +-- b_data_in8 <="11110100"; +-- state<="10000"; +-- elsif state="10000" then +-- b_done_n <='0'; +-- --b_data_in8 <="11110101"; +-- b_data_in8 <=b_addr16(7 downto 0); +-- if not l2b_al(b_cs_n) then +-- state<="00001"; +-- b_data_in8 <="11110110"; +-- end if; +-- else +-- state<="00001"; +-- end if; +-- end if; +-- end process; +-- + + + + + b_data_in(7 downto 0) <= b_data_out8; + b_data_in(15 downto 8) <= (others =>'0'); + b_data_in8 <= b_data_out(7 downto 0); + b_addr(15 downto 0) <= b_addr16; b_addr(23 downto 16) <= (others => '0'); + sdram_ctrl0: sdram_ctrl port map ( - clock_100 => clock_50, + clock_100 => clock_100, reset_n => b_reset_n, bus_cs_n => b_cs_n, bus_rnw => b_rnw, - bus_wait_n => b_wait_n, + bus_done_n => b_done_n, bus_addr => b_addr, bus_data_in => b_data_in, diff --git a/sdram_test_mcu.qsys b/sdram_test_mcu.qsys index 087e972..fd24a58 100644 --- a/sdram_test_mcu.qsys +++ b/sdram_test_mcu.qsys @@ -12,11 +12,11 @@ element $${FILENAME} { } - element async_16bit_bus_adapter_0 + element async_8bit_bus_adapter_0 { datum _sortIndex { - value = "6"; + value = "7"; type = "int"; } } @@ -24,15 +24,15 @@ { datum baseAddress { - value = "270432"; + value = "172128"; type = "String"; } } - element async_16bit_bus_adapter_0.avalon_slave + element async_8bit_bus_adapter_0.avalon_slave { datum baseAddress { - value = "131072"; + value = "65536"; type = "String"; } } @@ -48,7 +48,7 @@ { datum baseAddress { - value = "266240"; + value = "167936"; type = "String"; } } @@ -69,7 +69,7 @@ { datum baseAddress { - value = "268288"; + value = "169984"; type = "String"; } } @@ -89,6 +89,14 @@ type = "int"; } } + element onchip_memory2_0 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } element pio_0 { datum _sortIndex @@ -97,19 +105,27 @@ type = "int"; } } - element timer_0.s1 + element pio_0.s1 { datum baseAddress { - value = "270368"; + value = "172112"; type = "String"; } } - element pio_0.s1 + element onchip_memory2_0.s1 + { + datum baseAddress + { + value = "147456"; + type = "String"; + } + } + element timer_0.s1 { datum baseAddress { - value = "270416"; + value = "172064"; type = "String"; } } @@ -131,12 +147,12 @@ <parameter name="generateLegacySim" value="false" /> <parameter name="generationId" value="0" /> <parameter name="globalResetBus" value="false" /> - <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hdlLanguage" value="VHDL" /> <parameter name="maxAdditionalLatency" value="1" /> <parameter name="projectName" value="sdram_test.qpf" /> <parameter name="sopcBorderPoints" value="false" /> <parameter name="systemHash" value="1" /> - <parameter name="timeStamp" value="1381777663717" /> + <parameter name="timeStamp" value="1381799971798" /> <parameter name="useTestBenchNamingPattern" value="false" /> <instanceScript></instanceScript> <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> @@ -147,8 +163,8 @@ type="conduit" dir="end" /> <interface - name="sbb_0" - internal="async_16bit_bus_adapter_0.sbb" + name="ebb_0" + internal="async_8bit_bus_adapter_0.eight_bit_bus" type="conduit" dir="end" /> <module kind="clock_source" version="13.0" enabled="1" name="clk_0"> @@ -215,9 +231,9 @@ <parameter name="cpuID_stored" value="0" /> <parameter name="breakOffset" value="32" /> <parameter name="userDefinedSettings" value="" /> - <parameter name="resetSlave">async_16bit_bus_adapter_0.avalon_slave</parameter> + <parameter name="resetSlave" value="onchip_memory2_0.s1" /> <parameter name="mmu_TLBMissExcSlave" value="" /> - <parameter name="exceptionSlave">async_16bit_bus_adapter_0.avalon_slave</parameter> + <parameter name="exceptionSlave" value="onchip_memory2_0.s1" /> <parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter> <parameter name="setting_perfCounterWidth" value="32" /> <parameter name="setting_interruptControllerType" value="Internal" /> @@ -252,8 +268,8 @@ <parameter name="ocimem_ramBlockType" value="Automatic" /> <parameter name="mmu_ramBlockType" value="Automatic" /> <parameter name="bht_ramBlockType" value="Automatic" /> - <parameter name="instAddrWidth" value="19" /> - <parameter name="dataAddrWidth" value="19" /> + <parameter name="instAddrWidth" value="18" /> + <parameter name="dataAddrWidth" value="18" /> <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" /> <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" /> <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" /> @@ -262,8 +278,8 @@ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" /> - <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='async_16bit_bus_adapter_0.avalon_slave' start='0x20000' end='0x40000' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x41000' end='0x41800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x41800' end='0x42000' /><slave name='timer_0.s1' start='0x42020' end='0x42040' /><slave name='pio_0.s1' start='0x42050' end='0x42060' /></address-map>]]></parameter> - <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='async_16bit_bus_adapter_0.avalon_slave' start='0x20000' end='0x40000' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x41000' end='0x41800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x41800' end='0x42000' /><slave name='timer_0.s1' start='0x42020' end='0x42040' /><slave name='pio_0.s1' start='0x42050' end='0x42060' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x42060' end='0x42068' /></address-map>]]></parameter> + <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26F08' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29000' end='0x29800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='pio_0.s1' start='0x2A050' end='0x2A060' /></address-map>]]></parameter> + <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26F08' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29000' end='0x29800' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='pio_0.s1' start='0x2A050' end='0x2A060' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A060' end='0x2A068' /></address-map>]]></parameter> <parameter name="clockFrequency" value="80000000" /> <parameter name="deviceFamilyName" value="Cyclone II" /> <parameter name="internalIrqMaskSystemInfo" value="7" /> @@ -341,12 +357,37 @@ <parameter name="avalonSpec" value="2.0" /> </module> <module - kind="async_16bit_bus_adapter" + kind="altera_avalon_onchip_memory2" + version="13.0.1.99.2" + enabled="1" + name="onchip_memory2_0"> + <parameter name="allowInSystemMemoryContentEditor" value="false" /> + <parameter name="blockType" value="AUTO" /> + <parameter name="dataWidth" value="32" /> + <parameter name="dualPort" value="false" /> + <parameter name="initMemContent" value="true" /> + <parameter name="initializationFileName" value="onchip_mem.hex" /> + <parameter name="instanceID" value="NONE" /> + <parameter name="memorySize" value="12040" /> + <parameter name="readDuringWriteMode" value="DONT_CARE" /> + <parameter name="simAllowMRAMContentsFile" value="false" /> + <parameter name="simMemInitOnlyFilename" value="0" /> + <parameter name="singleClockOperation" value="false" /> + <parameter name="slave1Latency" value="1" /> + <parameter name="slave2Latency" value="1" /> + <parameter name="useNonDefaultInitFile" value="false" /> + <parameter name="useShallowMemBlocks" value="false" /> + <parameter name="writable" value="true" /> + <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter> + <parameter name="deviceFamily" value="Cyclone II" /> + <parameter name="deviceFeatures">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter> + </module> + <module + kind="async_8bit_bus_adapter" version="1.0" enabled="1" - name="async_16bit_bus_adapter_0"> - <parameter name="AUTO_CLOCK_CLOCK_RATE" value="-1" /> - <parameter name="AUTO_CLOCK_CLOCK_RATE_1" value="80000000" /> + name="async_8bit_bus_adapter_0"> + <parameter name="AUTO_CLOCK_CLOCK_RATE" value="80000000" /> </module> <connection kind="avalon" @@ -354,7 +395,7 @@ start="nios2_qsys_0.instruction_master" end="nios2_qsys_0.jtag_debug_module"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00041800" /> + <parameter name="baseAddress" value="0x00029800" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -363,7 +404,7 @@ start="nios2_qsys_0.data_master" end="nios2_qsys_0.jtag_debug_module"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00041800" /> + <parameter name="baseAddress" value="0x00029800" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -398,7 +439,7 @@ start="nios2_qsys_0.instruction_master" end="epcs_flash_controller_0.epcs_control_port"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00041000" /> + <parameter name="baseAddress" value="0x00029000" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -407,7 +448,7 @@ start="nios2_qsys_0.data_master" end="epcs_flash_controller_0.epcs_control_port"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00041000" /> + <parameter name="baseAddress" value="0x00029000" /> <parameter name="defaultConnection" value="false" /> </connection> <connection kind="clock" version="13.0" start="clk_0.clk" end="timer_0.clk" /> @@ -427,7 +468,7 @@ start="nios2_qsys_0.data_master" end="timer_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00042020" /> + <parameter name="baseAddress" value="0x0002a020" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -436,7 +477,7 @@ start="nios2_qsys_0.instruction_master" end="timer_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00042020" /> + <parameter name="baseAddress" value="0x0002a020" /> <parameter name="defaultConnection" value="false" /> </connection> <connection kind="clock" version="13.0" start="clk_0.clk" end="pio_0.clk" /> @@ -447,7 +488,7 @@ start="nios2_qsys_0.data_master" end="pio_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00042050" /> + <parameter name="baseAddress" value="0x0002a050" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -456,7 +497,7 @@ start="nios2_qsys_0.instruction_master" end="pio_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00042050" /> + <parameter name="baseAddress" value="0x0002a050" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -481,7 +522,7 @@ start="nios2_qsys_0.data_master" end="jtag_uart_0.avalon_jtag_slave"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00042060" /> + <parameter name="baseAddress" value="0x0002a060" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -509,35 +550,68 @@ kind="clock" version="13.0" start="clk_0.clk" - end="async_16bit_bus_adapter_0.clock" /> + end="onchip_memory2_0.clk1" /> <connection kind="avalon" version="13.0" start="nios2_qsys_0.data_master" - end="async_16bit_bus_adapter_0.avalon_slave"> + end="onchip_memory2_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00020000" /> + <parameter name="baseAddress" value="0x00024000" /> <parameter name="defaultConnection" value="false" /> </connection> <connection kind="avalon" version="13.0" start="nios2_qsys_0.instruction_master" - end="async_16bit_bus_adapter_0.avalon_slave"> + end="onchip_memory2_0.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00020000" /> + <parameter name="baseAddress" value="0x00024000" /> <parameter name="defaultConnection" value="false" /> </connection> <connection kind="reset" version="13.0" start="nios2_qsys_0.jtag_debug_module_reset" - end="async_16bit_bus_adapter_0.reset" /> + end="onchip_memory2_0.reset1" /> + <connection + kind="reset" + version="13.0" + start="clk_0.clk_reset" + end="onchip_memory2_0.reset1" /> + <connection + kind="clock" + version="13.0" + start="clk_0.clk" + end="async_8bit_bus_adapter_0.clock" /> <connection kind="reset" version="13.0" start="clk_0.clk_reset" - end="async_16bit_bus_adapter_0.reset" /> + end="async_8bit_bus_adapter_0.reset" /> + <connection + kind="reset" + version="13.0" + start="nios2_qsys_0.jtag_debug_module_reset" + end="async_8bit_bus_adapter_0.reset" /> + <connection + kind="avalon" + version="13.0" + start="nios2_qsys_0.instruction_master" + end="async_8bit_bus_adapter_0.avalon_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00010000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="13.0" + start="nios2_qsys_0.data_master" + end="async_8bit_bus_adapter_0.avalon_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00010000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> </system> |