diff options
Diffstat (limited to 'sdram_test.vhd')
| -rw-r--r-- | sdram_test.vhd | 82 |
1 files changed, 63 insertions, 19 deletions
diff --git a/sdram_test.vhd b/sdram_test.vhd index 7fa6729..c916ee2 100644 --- a/sdram_test.vhd +++ b/sdram_test.vhd @@ -46,13 +46,13 @@ component sdram_test_mcu is clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n pio_0_d_export : out std_logic_vector(7 downto 0); -- export - sbb_0_reset_n : out std_logic; -- reset_n - sbb_0_cs_n : out std_logic; -- cs_n - sbb_0_rnw : out std_logic; -- rnw - sbb_0_wait_n : in std_logic := 'X'; -- wait_n - sbb_0_addr : out std_logic_vector(15 downto 0); -- addr - sbb_0_data_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- data_in - sbb_0_data_out : out std_logic_vector(15 downto 0) -- data_out + ebb_0_cs_n : out std_logic; -- cs_n + ebb_0_rnw : out std_logic; -- rnw + ebb_0_done_n : in std_logic := 'X'; -- done_n + ebb_0_addr : out std_logic_vector(15 downto 0); -- addr + ebb_0_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_in + ebb_0_data_out : out std_logic_vector(7 downto 0); -- data_out + ebb_0_reset_n : out std_logic -- reset_n ); end component sdram_test_mcu; @@ -65,7 +65,7 @@ component sdram_ctrl is bus_cs_n : in std_logic; bus_rnw : in std_logic; - bus_wait_n : out std_logic; + bus_done_n : out std_logic; bus_addr : in addr_t; bus_data_in : in data_t; @@ -99,7 +99,7 @@ signal b_data_in : data_t; signal b_data_out : data_t; signal b_cs_n : std_logic; signal b_rnw : std_logic; -signal b_wait_n : std_logic; +signal b_done_n : std_logic; signal pll_reset : std_logic; signal mcu_clock : std_logic; @@ -110,8 +110,8 @@ signal debug : std_logic_vector(7 downto 0); signal global_reset_n : std_logic; signal b_reset_n : std_logic; -signal buf8 : std_logic_vector(7 downto 0); +signal state: std_logic_vector(4 downto 0); begin @@ -127,28 +127,72 @@ begin clk_clk => mcu_clock, -- clk.clk reset_reset_n => global_reset_n, -- reset.reset_n pio_0_d_export => seven_seg, -- pio_0_d.export - sbb_0_reset_n => b_reset_n, - sbb_0_cs_n => b_cs_n, -- ebb_0.cs_n - sbb_0_rnw => b_rnw, -- .rnw - sbb_0_wait_n => b_wait_n, -- .wait_n - sbb_0_addr => b_addr16, -- .addr - sbb_0_data_in => b_data_in, -- .data - sbb_0_data_out => b_data_out -- .data + ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n + ebb_0_rnw => b_rnw, -- .rnw + ebb_0_done_n => b_done_n, -- .done_n + ebb_0_addr => b_addr16, -- .addr + ebb_0_data_in => b_data_in8, -- .data + ebb_0_data_out => b_data_out8, -- .data + ebb_0_reset_n => b_reset_n ); -- bodge buses together +-- +-- fish: process (b_reset_n,b_addr16,b_cs_n,clock_100) begin +-- if l2b_al(b_reset_n) then +-- state <="00001"; +-- b_done_n <= '1'; +-- elsif rising_edge(clock_100) then +-- if state ="00001" then +-- b_done_n <='1'; +-- b_data_in8 <="11110001"; +-- if l2b_al(b_cs_n) then +-- state<="00010"; +-- end if; +-- elsif state="00010" then +-- b_data_in8 <="11110010"; +-- state<="00100"; +-- elsif state="00100" then +-- b_data_in8 <="11110011"; +-- state<="01000"; +-- elsif state="01000" then +-- b_data_in8 <="11110100"; +-- state<="10000"; +-- elsif state="10000" then +-- b_done_n <='0'; +-- --b_data_in8 <="11110101"; +-- b_data_in8 <=b_addr16(7 downto 0); +-- if not l2b_al(b_cs_n) then +-- state<="00001"; +-- b_data_in8 <="11110110"; +-- end if; +-- else +-- state<="00001"; +-- end if; +-- end if; +-- end process; +-- + + + + + b_data_in(7 downto 0) <= b_data_out8; + b_data_in(15 downto 8) <= (others =>'0'); + b_data_in8 <= b_data_out(7 downto 0); + b_addr(15 downto 0) <= b_addr16; b_addr(23 downto 16) <= (others => '0'); + sdram_ctrl0: sdram_ctrl port map ( - clock_100 => clock_50, + clock_100 => clock_100, reset_n => b_reset_n, bus_cs_n => b_cs_n, bus_rnw => b_rnw, - bus_wait_n => b_wait_n, + bus_done_n => b_done_n, bus_addr => b_addr, bus_data_in => b_data_in, |