diff options
Diffstat (limited to 'sdram_ctrl.vhd')
| -rw-r--r-- | sdram_ctrl.vhd | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd index b0b4a1f..1a54fc3 100644 --- a/sdram_ctrl.vhd +++ b/sdram_ctrl.vhd @@ -17,7 +17,7 @@ entity sdram_ctrl is bus_cs_n : in std_logic; bus_rnw : in std_logic; - bus_wait_n : out std_logic; + bus_done_n : out std_logic; bus_addr : in addr_t; bus_data_in : in data_t; @@ -549,11 +549,12 @@ begin b_state <= B_ST_WAIT_CS_N_LOW; b_debug(6 downto 0) <= DEBUG_0; b_debug(7) <='0'; - bus_wait_n <= '0'; + bus_done_n <= '1'; elsif rising_edge(clock) then if b_state = B_ST_WAIT_CS_N_LOW then b_debug(6 downto 0) <= DEBUG_1; - bus_wait_n <= '0'; + bus_done_n <= '1'; +-- bus_data_out <="1111000111110001"; if l2b_al(bus_cs_n) then -- new request ship it to the main state machine post_request <='1'; @@ -577,6 +578,7 @@ begin -- the logic has pushed the request to the ram if l2b_al(request_rnw) then -- if it's a write we're all done + bus_done_n <='0'; b_state <= B_ST_WAIT_CS_N_HIGH; else -- if it's a read we have to wait for the data @@ -587,14 +589,17 @@ begin b_debug(6 downto 0) <= DEBUG_4; if l2b_ah(r_data_valid(0)) then bus_data_out <= mem_data_in; --- bus_data_out <= request_addr(15 downto 0); + bus_done_n <= '0'; + --bus_data_out <= request_addr(15 downto 0); + --bus_data_out <= bus_addr(15 downto 0); b_state <= B_ST_WAIT_CS_N_HIGH; end if; elsif b_state = B_ST_WAIT_CS_N_HIGH then b_debug(6 downto 0) <= DEBUG_5; b_debug(7) <='1'; - bus_wait_n <= '1'; if not l2b_al(bus_cs_n) then +-- bus_data_out <="1111001011110010"; + bus_done_n <= '1'; b_state <=B_ST_WAIT_CS_N_LOW; end if; else |