checksumfail

1 files changed, 5 insertions, 5 deletions

diff --git a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
index 9c8a806..715123f 100644
--- a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
+++ b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
@@ -1,4 +1,4 @@
--- async_8bit_bus_adapter.vhd
+-- async_16bit_bus_adapter.vhd
 
 -- This file was auto-generated as a prototype implementation of a module
 -- created in component editor.  It ties off all outputs to ground and
@@ -12,7 +12,7 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
-entity async_8bit_bus_adapter is
+entity async_16bit_bus_adapter is
 	generic (
 		AUTO_CLOCK_CLOCK_RATE : string := "-1"
 	);
@@ -34,9 +34,9 @@ entity async_8bit_bus_adapter is
 		b_data_in  : in  std_logic_vector(15 downto 0)  := (others => '0'); --              .export
 		b_data_out : out std_logic_vector(15 downto 0)                      --              .export
 	);
-end entity async_8bit_bus_adapter;
+end entity async_16bit_bus_adapter;
 
-architecture rtl of async_8bit_bus_adapter is
+architecture rtl of async_16bit_bus_adapter is
 
 signal state:std_logic_vector(2 downto 0);
 begin
@@ -51,4 +51,4 @@ begin
 	wait_n <= b_wait_n;
 
 
-end architecture rtl; -- of async_8bit_bus_adapter
+end architecture rtl; -- of async_16bit_bus_adapter