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-- async_8bit_bus_adapter.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity async_8bit_bus_adapter is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1"
);
port (
clk : in std_logic := '0'; -- clock.clk
rst_n : in std_logic := '0'; -- reset.reset_n
cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n
address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
wr_n : in std_logic := '0'; -- .write_n
rd_n : in std_logic := '0'; -- .read_n
wait_n : out std_logic; -- .waitrequest_n
readdata : out std_logic_vector(15 downto 0); -- .readdata
b_reset_n : out std_logic; -- eight_bit_bus.export
b_cs_n : out std_logic; -- .export
b_rnw : out std_logic; -- .export
b_wait_n : in std_logic := '0'; -- .export
b_addr : out std_logic_vector(15 downto 0); -- .export
b_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- .export
b_data_out : out std_logic_vector(15 downto 0) -- .export
);
end entity async_8bit_bus_adapter;
architecture rtl of async_8bit_bus_adapter is
signal state:std_logic_vector(2 downto 0);
begin
b_addr <= address;
readdata <= b_data_in;
b_data_out <= writedata;
b_reset_n <= rst_n;
b_cs_n <= cs_n or ( wr_n and rd_n );
b_rnw <= wr_n;
wait_n <= b_wait_n;
end architecture rtl; -- of async_8bit_bus_adapter
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