checksumfail

4 files changed, 30 insertions, 29 deletions

diff --git a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl
index d18a0ed..08709ff 100644
--- a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl
+++ b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 13.0sp1
-# Mon Oct 14 19:47:04 BST 2013
+# Mon Oct 14 20:08:19 BST 2013
 # DO NOT MODIFY
 
 
 # 
 # async_16bit_bus_adapter "async_16bit_bus_adapter" v1.0
-#  2013.10.14.19:47:04
+#  2013.10.14.20:08:19
 # 
 # 
 
@@ -85,6 +85,7 @@ set_interface_property avalon_slave burstOnBurstBoundariesOnly false
 set_interface_property avalon_slave burstcountUnits WORDS
 set_interface_property avalon_slave explicitAddressSpan 0
 set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave isMemoryDevice true
 set_interface_property avalon_slave linewrapBursts false
 set_interface_property avalon_slave maximumPendingReadTransactions 0
 set_interface_property avalon_slave readLatency 0
@@ -105,7 +106,7 @@ add_interface_port avalon_slave rd_n read_n Input 1
 add_interface_port avalon_slave wait_n waitrequest_n Output 1
 add_interface_port avalon_slave readdata readdata Output 16
 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
-set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 1
 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
 
diff --git a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
index 9c8a806..715123f 100644
--- a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
+++ b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd
@@ -1,4 +1,4 @@
--- async_8bit_bus_adapter.vhd
+-- async_16bit_bus_adapter.vhd
 
 -- This file was auto-generated as a prototype implementation of a module
 -- created in component editor.  It ties off all outputs to ground and
@@ -12,7 +12,7 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
-entity async_8bit_bus_adapter is
+entity async_16bit_bus_adapter is
 	generic (
 		AUTO_CLOCK_CLOCK_RATE : string := "-1"
 	);
@@ -34,9 +34,9 @@ entity async_8bit_bus_adapter is
 		b_data_in  : in  std_logic_vector(15 downto 0)  := (others => '0'); --              .export
 		b_data_out : out std_logic_vector(15 downto 0)                      --              .export
 	);
-end entity async_8bit_bus_adapter;
+end entity async_16bit_bus_adapter;
 
-architecture rtl of async_8bit_bus_adapter is
+architecture rtl of async_16bit_bus_adapter is
 
 signal state:std_logic_vector(2 downto 0);
 begin
@@ -51,4 +51,4 @@ begin
 	wait_n <= b_wait_n;
 
 
-end architecture rtl; -- of async_8bit_bus_adapter
+end architecture rtl; -- of async_16bit_bus_adapter
diff --git a/sdram_test.vhd b/sdram_test.vhd
index 156ca28..7fa6729 100644
--- a/sdram_test.vhd
+++ b/sdram_test.vhd
@@ -5,7 +5,7 @@ use IEEE.NUMERIC_STD.ALL;
 library work;
 use work.sdram_util.ALL;
 
-entity sdram is
+entity sdram_test is
 port (
 	clock_50	:	in	std_logic;	
 	reset_n		:	in	std_logic;
@@ -27,7 +27,7 @@ port (
 );
 end entity;
 
-architecture rtl of sdram is
+architecture rtl of sdram_test is
 
 component pllx2 IS
         PORT
@@ -46,15 +46,15 @@ component sdram_test_mcu is
 		clk_clk		: in    std_logic                     := 'X';             -- clk
 		reset_reset_n	: in    std_logic                     := 'X';             -- reset_n
 		pio_0_d_export	: out   std_logic_vector(7 downto 0);                     -- export
-		sbb_0_reset_n	: out   std_logic                                        -- reset_n
+		sbb_0_reset_n	: out   std_logic;                                        -- reset_n
 		sbb_0_cs_n	: out   std_logic;                                        -- cs_n
 		sbb_0_rnw	: out   std_logic;                                        -- rnw
 		sbb_0_wait_n	: in    std_logic                     := 'X';             -- wait_n
 		sbb_0_addr	: out   std_logic_vector(15 downto 0);                    -- addr
 		sbb_0_data_in	: in    std_logic_vector(15 downto 0)  := (others => 'X'); -- data_in
-		sbb_0_data_out	: out   std_logic_vector(15 downto 0);                     -- data_out
+		sbb_0_data_out	: out   std_logic_vector(15 downto 0)                     -- data_out
 	);
-end component sdram_mcu;
+end component sdram_test_mcu;
 
 component sdram_ctrl is
   port
@@ -123,17 +123,17 @@ begin
 
 	mcu_clock <= clock_50;
 
-   	u0 : component sdram_mcu port map (
+   	u0 : component sdram_test_mcu port map (
 		clk_clk        => mcu_clock,        --     clk.clk
 		reset_reset_n  => global_reset_n,  --   reset.reset_n
 		pio_0_d_export => seven_seg, -- pio_0_d.export
-		sbb_0_reset_n   => b_reset_n  
+		sbb_0_reset_n   => b_reset_n,  
 		sbb_0_cs_n      => b_cs_n,      --    ebb_0.cs_n
 		sbb_0_rnw       => b_rnw,      --        .rnw
 		sbb_0_wait_n    => b_wait_n,    --        .wait_n
 		sbb_0_addr      => b_addr16,      --        .addr
 		sbb_0_data_in   => b_data_in,   --        .data
-		sbb_0_data_out  => b_data_out,   --        .data
+		sbb_0_data_out  => b_data_out   --        .data
 	);
 
  	-- bodge buses together
diff --git a/sdram_test_mcu.qsys b/sdram_test_mcu.qsys
index c0cba01..087e972 100644
--- a/sdram_test_mcu.qsys
+++ b/sdram_test_mcu.qsys
@@ -136,7 +136,7 @@
  <parameter name="projectName" value="sdram_test.qpf" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1381776549910" />
+ <parameter name="timeStamp" value="1381777663717" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
@@ -511,19 +511,9 @@
    start="clk_0.clk"
    end="async_16bit_bus_adapter_0.clock" />
  <connection
-   kind="reset"
-   version="13.0"
-   start="clk_0.clk_reset"
-   end="async_16bit_bus_adapter_0.reset" />
- <connection
-   kind="reset"
-   version="13.0"
-   start="nios2_qsys_0.jtag_debug_module_reset"
-   end="async_16bit_bus_adapter_0.reset" />
- <connection
    kind="avalon"
    version="13.0"
-   start="nios2_qsys_0.instruction_master"
+   start="nios2_qsys_0.data_master"
    end="async_16bit_bus_adapter_0.avalon_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00020000" />
@@ -532,12 +522,22 @@
  <connection
    kind="avalon"
    version="13.0"
-   start="nios2_qsys_0.data_master"
+   start="nios2_qsys_0.instruction_master"
    end="async_16bit_bus_adapter_0.avalon_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x00020000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="nios2_qsys_0.jtag_debug_module_reset"
+   end="async_16bit_bus_adapter_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_0.clk_reset"
+   end="async_16bit_bus_adapter_0.reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
 </system>