diff options
Diffstat (limited to 'sdram_test.vhd')
| -rw-r--r-- | sdram_test.vhd | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/sdram_test.vhd b/sdram_test.vhd index 156ca28..7fa6729 100644 --- a/sdram_test.vhd +++ b/sdram_test.vhd @@ -5,7 +5,7 @@ use IEEE.NUMERIC_STD.ALL; library work; use work.sdram_util.ALL; -entity sdram is +entity sdram_test is port ( clock_50 : in std_logic; reset_n : in std_logic; @@ -27,7 +27,7 @@ port ( ); end entity; -architecture rtl of sdram is +architecture rtl of sdram_test is component pllx2 IS PORT @@ -46,15 +46,15 @@ component sdram_test_mcu is clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n pio_0_d_export : out std_logic_vector(7 downto 0); -- export - sbb_0_reset_n : out std_logic -- reset_n + sbb_0_reset_n : out std_logic; -- reset_n sbb_0_cs_n : out std_logic; -- cs_n sbb_0_rnw : out std_logic; -- rnw sbb_0_wait_n : in std_logic := 'X'; -- wait_n sbb_0_addr : out std_logic_vector(15 downto 0); -- addr sbb_0_data_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- data_in - sbb_0_data_out : out std_logic_vector(15 downto 0); -- data_out + sbb_0_data_out : out std_logic_vector(15 downto 0) -- data_out ); -end component sdram_mcu; +end component sdram_test_mcu; component sdram_ctrl is port @@ -123,17 +123,17 @@ begin mcu_clock <= clock_50; - u0 : component sdram_mcu port map ( + u0 : component sdram_test_mcu port map ( clk_clk => mcu_clock, -- clk.clk reset_reset_n => global_reset_n, -- reset.reset_n pio_0_d_export => seven_seg, -- pio_0_d.export - sbb_0_reset_n => b_reset_n + sbb_0_reset_n => b_reset_n, sbb_0_cs_n => b_cs_n, -- ebb_0.cs_n sbb_0_rnw => b_rnw, -- .rnw sbb_0_wait_n => b_wait_n, -- .wait_n sbb_0_addr => b_addr16, -- .addr sbb_0_data_in => b_data_in, -- .data - sbb_0_data_out => b_data_out, -- .data + sbb_0_data_out => b_data_out -- .data ); -- bodge buses together |