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authorroot <root@artemis.panaceas.org>2013-10-14 19:49:09 +0100
committerroot <root@artemis.panaceas.org>2013-10-14 19:49:09 +0100
commitd7aa862be9e4a3093b1a29a1bed4267415b89b46 (patch)
treec5c6961a5445ca6a95ba2ec0f91703c105544c70
parent104aa43eb164408901fed3dbc499be79f24db224 (diff)
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-rw-r--r--sdram.vhd2
-rw-r--r--sdram_ctrl.vhd10
2 files changed, 5 insertions, 7 deletions
diff --git a/sdram.vhd b/sdram.vhd
index c0cb4ef..f363ea3 100644
--- a/sdram.vhd
+++ b/sdram.vhd
@@ -165,7 +165,7 @@ begin
sdram_ctrl0: sdram_ctrl port map (
- clock_100 => clock_100,
+ clock_100 => clock_50,
reset_n => b_reset_n,
bus_cs_n => b_cs_n,
diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd
index 58064bd..b0b4a1f 100644
--- a/sdram_ctrl.vhd
+++ b/sdram_ctrl.vhd
@@ -149,7 +149,7 @@ architecture rtl of sdram_ctrl is
signal request_dqm : dqm_t;
-- read state logic
- signal r_data_valid: std_logic_vector(2 downto 0);
+ signal r_data_valid: std_logic_vector(3 downto 0);
-- bus logic
signal post_request: std_logic;
@@ -532,8 +532,8 @@ begin
if l2b_al(reset_n) then
r_data_valid <= (others => '0');
elsif rising_edge(clock) then
- r_data_valid(1 downto 0)<=r_data_valid(2 downto 1);
- r_data_valid(2) <= b2l_ah(mem_cmd = MEM_CMD_READ);
+ r_data_valid(2 downto 0)<=r_data_valid(3 downto 1);
+ r_data_valid(3) <= b2l_ah(mem_cmd = MEM_CMD_READ);
end if;
end process;
@@ -576,7 +576,6 @@ begin
if not l2b_ah(request_pending) then
-- the logic has pushed the request to the ram
if l2b_al(request_rnw) then
- bus_wait_n <= '1';
-- if it's a write we're all done
b_state <= B_ST_WAIT_CS_N_HIGH;
else
@@ -589,14 +588,13 @@ begin
if l2b_ah(r_data_valid(0)) then
bus_data_out <= mem_data_in;
-- bus_data_out <= request_addr(15 downto 0);
- bus_wait_n <= '1';
b_state <= B_ST_WAIT_CS_N_HIGH;
end if;
elsif b_state = B_ST_WAIT_CS_N_HIGH then
b_debug(6 downto 0) <= DEBUG_5;
b_debug(7) <='1';
+ bus_wait_n <= '1';
if not l2b_al(bus_cs_n) then
- bus_wait_n <= '0';
b_state <=B_ST_WAIT_CS_N_LOW;
end if;
else