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| author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
| commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
| tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/qemu-mips/lowlevel_init.S | |
| download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip | |
Diffstat (limited to 'roms/u-boot/board/qemu-mips/lowlevel_init.S')
| -rw-r--r-- | roms/u-boot/board/qemu-mips/lowlevel_init.S | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/roms/u-boot/board/qemu-mips/lowlevel_init.S b/roms/u-boot/board/qemu-mips/lowlevel_init.S new file mode 100644 index 00000000..b0f70727 --- /dev/null +++ b/roms/u-boot/board/qemu-mips/lowlevel_init.S @@ -0,0 +1,40 @@ +/* Memory sub-system initialization code */ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set K0=3) + */ + li t1, 0x00000003 + mtc0 t1, CP0_CONFIG + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + jr ra + nop |