Initial import of qemu-2.4.1HEADmaster

3 files changed, 128 insertions, 0 deletions

diff --git a/roms/u-boot/board/qemu-mips/Makefile b/roms/u-boot/board/qemu-mips/Makefile
new file mode 100644
index 00000000..8040573f
--- /dev/null
+++ b/roms/u-boot/board/qemu-mips/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= qemu-mips.o
+obj-y	+= lowlevel_init.o
diff --git a/roms/u-boot/board/qemu-mips/lowlevel_init.S b/roms/u-boot/board/qemu-mips/lowlevel_init.S
new file mode 100644
index 00000000..b0f70727
--- /dev/null
+++ b/roms/u-boot/board/qemu-mips/lowlevel_init.S
@@ -0,0 +1,40 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set K0=3)
+	 */
+	li	t1, 0x00000003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	jr	ra
+	nop
diff --git a/roms/u-boot/board/qemu-mips/qemu-mips.c b/roms/u-boot/board/qemu-mips/qemu-mips.c
new file mode 100644
index 00000000..563044eb
--- /dev/null
+++ b/roms/u-boot/board/qemu-mips/qemu-mips.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2007
+ * Vlad Lungu vlad.lungu@windriver.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <netdev.h>
+
+phys_size_t initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return MEM_SIZE*1024*1024;
+}
+
+int checkboard(void)
+{
+	u32 proc_id;
+	u32 config1;
+
+	proc_id = read_c0_prid();
+	printf("Board: Qemu -M mips CPU: ");
+	switch (proc_id) {
+	case 0x00018000:
+		printf("4Kc");
+		break;
+	case 0x00018400:
+		printf("4KEcR1");
+		break;
+	case 0x00019000:
+		printf("4KEc");
+		break;
+	case 0x00019300:
+		config1 = read_c0_config1();
+		if (config1 & 1)
+			printf("24Kf");
+		else
+			printf("24Kc");
+		break;
+	case 0x00019500:
+		printf("34Kf");
+		break;
+	case 0x00000400:
+		printf("R4000");
+		break;
+	case 0x00018100:
+		config1 = read_c0_config1();
+		if (config1 & 1)
+			printf("5Kf");
+		else
+			printf("5Kc");
+		break;
+	case 0x000182a0:
+		printf("20Kc");
+		break;
+
+	default:
+		printf("unknown");
+	}
+	printf(" proc_id=0x%x\n", proc_id);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	set_io_port_base(0);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return ne2k_register();
+}