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| author | David Bauer <mail@david-bauer.net> | 2021-04-01 01:20:45 +0200 |
|---|---|---|
| committer | David Bauer <mail@david-bauer.net> | 2021-04-13 00:32:56 +0200 |
| commit | fbbad9a9a629b388626b477e6cd692c160f63fb3 (patch) | |
| tree | a77dc9299ce39dab11a689bc27bd909e32646347 /target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch | |
| parent | e85180d90ed01ef4fb89675702622a9cabf3b092 (diff) | |
| download | upstream-fbbad9a9a629b388626b477e6cd692c160f63fb3.tar.gz upstream-fbbad9a9a629b388626b477e6cd692c160f63fb3.tar.bz2 upstream-fbbad9a9a629b388626b477e6cd692c160f63fb3.zip | |
ath79: force SGMII SerDes mode to MAC operation
The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default.
This only allows for 1000 Mbit/s links, however when used with an SGMII
PHY in 100 Mbit/s link mode, the link remains dead.
This strictly has nothing to do with the SerDes calibration, however it
is done at the same point in the QCA reference U-Boot which is the
blueprint for everything happening here. As the current state is more or
less a hack, this should be fine.
This fixes the issues outlined above on a TP-Link EAP-225 Outdoor.
Reported-by: Tom Herbers <freifunk@tomherbers.de>
Tested-by: Tom Herbers <freifunk@tomherbers.de>
Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch')
| -rw-r--r-- | target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch b/target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch new file mode 100644 index 0000000000..bf7cbf2716 --- /dev/null +++ b/target/linux/ath79/patches-5.4/0040-ath79-sgmii-config.patch @@ -0,0 +1,9 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1376,5 +1376,6 @@ + + #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 + #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC 0x2 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ |