Last-Modified: Thu, 28 Aug 2025 12:54:34 GMT
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<div class='path'>path: <a href='/cgit.cgi/iCE40/yosys/log/?id=70c607d7dde23b709ffd36c47680cddcc4666fcd&amp;showmsg=1'>root</a>/<a href='/cgit.cgi/iCE40/yosys/log/frontends?id=70c607d7dde23b709ffd36c47680cddcc4666fcd&amp;showmsg=1'>frontends</a>/<a href='/cgit.cgi/iCE40/yosys/log/frontends/verilog?id=70c607d7dde23b709ffd36c47680cddcc4666fcd&amp;showmsg=1'>verilog</a></div><div class='content'><table class='list nowrap'><tr class='nohover'><th></th><th class='left'>Commit message (<a href='/cgit.cgi/iCE40/yosys/log/frontends/verilog?id=70c607d7dde23b709ffd36c47680cddcc4666fcd'>Collapse</a>)</th><th class='left'>Author</th><th class='left'>Age</th><th class='left'>Files</th><th class='left'>Lines</th></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=a67d63714be52e4a4f789c2a82b6283748db8902'>Fix handling of z_digit "?" and fix optimization of cmp with "z"</a></td><td>Clifford Wolf</td><td><span title='2019-09-13 13:39:39 +0200'>2019-09-13</span></td><td>1</td><td><span class='deletions'>-5</span>/<span class='insertions'>+1</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=855e6a9b9172e6817c9ff57f7041b09a1cc0367e'>Fix lexing of integer literals without radix</a></td><td>Clifford Wolf</td><td><span title='2019-09-13 10:19:58 +0200'>2019-09-13</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=7eb593829f62476598bb15c2fb903d50108e5274'>Fix lexing of integer literals, fixes #1364</a></td><td>Clifford Wolf</td><td><span title='2019-09-12 09:43:32 +0200'>2019-09-12</span></td><td>2</td><td><span class='deletions'>-3</span>/<span class='insertions'>+3</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=6d77236f3845cd8785e7bdd4da3c5ef966be6043'>substr() -&gt; compare()</a></td><td>Eddie Hung</td><td><span title='2019-08-07 12:20:08 -0700'>2019-08-07</span></td><td>1</td><td><span class='deletions'>-4</span>/<span class='insertions'>+4</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=71649969213863b2695f1c51956886fc7879c3e6'>RTLIL::S{0,1} -&gt; State::S{0,1}</a></td><td>Eddie Hung</td><td><span title='2019-08-07 11:12:38 -0700'>2019-08-07</span></td><td>1</td><td><span class='deletions'>-12</span>/<span class='insertions'>+12</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=92694ea3a997cc6d081b6896c213d308adb466d5'>verilog_lexer: Increase YY_BUF_SIZE to 65536</a></td><td>David Shah</td><td><span title='2019-07-26 13:35:39 +0100'>2019-07-26</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+3</span></td></tr>
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Signed-off-by: David Shah &lt;dave@ds0.me&gt;


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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=e38b2ac64860704f18e1097a6db32260f41717c3'>Merge pull request #1147 from YosysHQ/clifford/fix1144</a></td><td>Clifford Wolf</td><td><span title='2019-07-03 12:30:37 +0200'>2019-07-03</span></td><td>1</td><td><span class='deletions'>-81</span>/<span class='insertions'>+14</span></td></tr>
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Improve specify dummy parser

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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=ba365679082cff2b9879eef5349bfdf2b5291449'>Some cleanups in "ignore specify parser"</a></td><td>Clifford Wolf</td><td><span title='2019-07-03 11:22:10 +0200'>2019-07-03</span></td><td>1</td><td><span class='deletions'>-79</span>/<span class='insertions'>+5</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=af744097496702926f4fbff5d6eb889ad82fa6cf'>Improve specify dummy parser, fixes #1144</a></td><td>Clifford Wolf</td><td><span title='2019-06-28 10:21:16 +0200'>2019-06-28</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+9</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=d206eca03b8aa7bb982fb2486c02c90a61354066'>Fix read_verilog assert/assume/etc on default case label, fixes ↵</a></td><td>Clifford Wolf</td><td><span title='2019-07-02 11:36:26 +0200'>2019-07-02</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+2</span></td></tr>
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YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=f6053b88103bfc652dec1959f30bfb1880613f61'>Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131</a></td><td>Clifford Wolf</td><td><span title='2019-06-26 11:09:43 +0200'>2019-06-26</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=78e7a6f6f25c57ba560613f978ef8d9281fb615a'>Merge pull request #1119 from YosysHQ/eddie/fix1118</a></td><td>Clifford Wolf</td><td><span title='2019-06-21 10:13:13 +0200'>2019-06-21</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+1</span></td></tr>
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Make genvar a signed type

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<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=c27ab609faeeb3ae9372ea4cf85e5ac6ba029646'>Make genvar a signed type</a></td><td>Eddie Hung</td><td><span title='2019-06-20 16:04:12 -0700'>2019-06-20</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+1</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=20119ee50e0cefbcd89275101c8710febd5afd32'>Maintain "is_unsized" state of constants</a></td><td>Eddie Hung</td><td><span title='2019-06-20 12:43:39 -0700'>2019-06-20</span></td><td>1</td><td><span class='deletions'>-6</span>/<span class='insertions'>+6</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=2428fb7dc2c2f24eab0d4283358e4eb7e8373146'>Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵</a></td><td>Clifford Wolf</td><td><span title='2019-06-20 12:03:00 +0200'>2019-06-20</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+7</span></td></tr>
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towoe-unpacked_arrays


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<tr class='logheader'><td class='commitgraph'><span class='column6'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=8b8af10f5e612eb1a39320e20b2d1d6f1e7d45df'>Unpacked array declaration using size</a></td><td>Tobias Wölfel</td><td><span title='2019-06-19 12:47:48 +0200'>2019-06-19</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+7</span></td></tr>
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Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.


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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=ec4565009ae69409eb01f1b595f5f59fcc969ce2'>Add "read_verilog -pwires" feature, closes #1106</a></td><td>Clifford Wolf</td><td><span title='2019-06-19 14:38:50 +0200'>2019-06-19</span></td><td>2</td><td><span class='deletions'>-3</span>/<span class='insertions'>+15</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe'>Add defaultvalue attribute</a></td><td>Clifford Wolf</td><td><span title='2019-06-19 11:37:11 +0200'>2019-06-19</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+11</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=6d64e242ba8214f7bceb35f688b544f56d49cea1'>Fix handling of "logic" variables with initial value</a></td><td>Clifford Wolf</td><td><span title='2019-06-19 11:25:11 +0200'>2019-06-19</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=4b56f6646dbf819da9fa1fdd47bb4bbdf943be7f'>Fixed brojen $error()/$info/$warning() on non-generate blocks</a></td><td>Udi Finkelstein</td><td><span title='2019-06-11 02:52:06 +0300'>2019-06-11</span></td><td>2</td><td><span class='deletions'>-3</span>/<span class='insertions'>+13</span></td></tr>
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(within always/initial blocks)


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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=a3bbc5365bc8ed411ab437a6baea5596531933a8'>Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵</a></td><td>Clifford Wolf</td><td><span title='2019-06-07 12:08:42 +0200'>2019-06-07</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+15</span></td></tr>
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clifford/pr983


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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=ac10e7d96da4965751fd60a8dd42a8998c011c39'>Initial implementation of elaboration system tasks</a></td><td>Udi Finkelstein</td><td><span title='2019-05-03 03:10:43 +0300'>2019-05-03</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+15</span></td></tr>
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<span class='column2'>|</span> <span class='column3'>|</span> 
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<td colspan='5' class='logmsg'>
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=a0b57f2a6ffae3b5770e38bf5a9af0df50db8522'>Cleanup tux3-implicit_named_connection</a></td><td>Clifford Wolf</td><td><span title='2019-06-07 11:46:16 +0200'>2019-06-07</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column3'>|</span> <span class='column3'>|</span> 
<span class='column3'>|</span> <span class='column3'>|</span> 
<span class='column3'>|</span> <span class='column3'>|</span> 
<span class='column3'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=b637b3109d61ff2d120978975a7b8cdc2ca3f418'>Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵</a></td><td>Clifford Wolf</td><td><span title='2019-06-07 11:41:54 +0200'>2019-06-07</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+10</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span><span class='column5'>\</span> <span class='column3'>\</span>  
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
into tux3-implicit_named_connection


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=88f59770932720cfc1e987c98e53faedd7388ed8'>SystemVerilog support for implicit named port connections</a></td><td>tux3</td><td><span title='2019-06-06 18:07:49 +0200'>2019-06-06</span></td><td>1</td><td><span class='deletions'>-9</span>/<span class='insertions'>+17</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
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<td colspan='5' class='logmsg'>
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=03e0d3a17cf27858d16e0169614b6575c7dac538'>Fixed memory leak.</a></td><td>Maciej Kurc</td><td><span title='2019-06-05 10:42:43 +0200'>2019-06-05</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+4</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Maciej Kurc &lt;mkurc@antmicro.com&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=a6cadf6318f4eff6197d6c6f0e052c2417689f38'>Added support for parsing attributes on port connections.</a></td><td>Maciej Kurc</td><td><span title='2019-05-31 14:58:43 +0200'>2019-05-31</span></td><td>1</td><td><span class='deletions'>-10</span>/<span class='insertions'>+10</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span><span class='column5'>/</span> <span class='column3'>/</span>  
<span class='column5'>|</span> <span class='column3'>|</span>   
<span class='column5'>|</span> <span class='column3'>|</span>   
<span class='column5'>|</span> <span class='column3'>|</span>   </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Maciej Kurc &lt;mkurc@antmicro.com&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=816082d5a11e758b6ff68a2dc442fc2519356669'>Merge branch 'master' into wandwor</a></td><td>Stefan Biereigel</td><td><span title='2019-05-27 19:07:46 +0200'>2019-05-27</span></td><td>2</td><td><span class='deletions'>-9</span>/<span class='insertions'>+19</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column6'>|</span><span class='column1'>\</span> <span class='column3'>\</span>  </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column6'>|</span> * <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=34417ce55f1b1d71ac11dfdfecfffc7a3340b6cb'>Added support for unsized constants, fixes #1022</a></td><td>Miodrag Milanovic</td><td><span title='2019-05-27 11:42:10 +0200'>2019-05-27</span></td><td>2</td><td><span class='deletions'>-9</span>/<span class='insertions'>+19</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column6'>|</span> <span class='column1'>|</span> <span class='column3'>|</span> 
<span class='column6'>|</span> <span class='column1'>|</span> <span class='column3'>|</span> 
<span class='column6'>|</span> <span class='column1'>|</span> <span class='column3'>|</span> 
<span class='column6'>|</span> <span class='column1'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Includes work from @sumit0190 and @AaronKel


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae'>fix indentation across files</a></td><td>Stefan Biereigel</td><td><span title='2019-05-23 13:57:27 +0200'>2019-05-23</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column1'>|</span> <span class='column1'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=9df04d7e7520884bfc40004bb131cfdb474061c7'>make lexer/parser aware of wand/wor net types</a></td><td>Stefan Biereigel</td><td><span title='2019-05-23 13:57:27 +0200'>2019-05-23</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+9</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column1'>|</span><span class='column1'>/</span> <span class='column3'>/</span>  </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=48ddbe52fb1428fc8f7f3d6444c5637eb151475f'>Read bigger Verilog files.</a></td><td>Kaj Tuomi</td><td><span title='2019-05-18 14:20:30 +0300'>2019-05-18</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column1'>|</span> <span class='column3'>|</span> 
<span class='column1'>|</span> <span class='column3'>|</span> 
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<td colspan='5' class='logmsg'>
Hit parser limit with 3M gate design. This commit fix it.


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=b6345b111d994ff0de1bcd91379db1c289feb03b'>Merge pull request #1013 from antmicro/parameter_attributes</a></td><td>Clifford Wolf</td><td><span title='2019-05-16 14:21:18 +0200'>2019-05-16</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span><span class='column3'>\</span> <span class='column3'>\</span>  
<span class='column2'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> 
<span class='column2'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Support for attributes on parameters and localparams for Verilog frontend

</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=ce4a0954bc896eedfc2d87e2c9d2b40f42a101db'>Added support for parsing attributes on parameters in Verilog frontent. ↵</a></td><td>Maciej Kurc</td><td><span title='2019-05-16 12:44:16 +0200'>2019-05-16</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> 
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<span class='column2'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> 
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<td colspan='5' cla<style>pre { line-height: 125%; margin: 0; }
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.highlight .ge { font-style</td><td>4</td><td><span class='deletions'>-33</span>/<span class='insertions'>+328</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span><span class='column5'>\</span> <span class='column3'>\</span>  
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> 
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Add specify parser

</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>\</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=c7f2e93024b7758a865254cfb350997645f663b2'>Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify</a></td><td>Clifford Wolf</td><td><span title='2019-05-06 11:46:10 +0200'>2019-05-06</span></td><td>2</td><td><span class='deletions'>-2</span>/<span class='insertions'>+10</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column6'>|</span><span class='column1'>\</span> <span class='column3'>\</span>  </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column1'>\</span> <span class='column3'>\</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=d9c4644e88b916d1eadfd401abf297c0995b6462'>Merge remote-tracking branch 'origin/master' into clifford/specify</a></td><td>Eddie Hung</td><td><span title='2019-05-03 15:05:57 -0700'>2019-05-03</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column2'>|</span><span class='column3'>\</span> <span class='column1'>\</span> <span class='column3'>\</span>  
<span class='column4'>|</span> <span class='column2'>|</span> <span class='column3'>|</span> <span class='column1'>|</span><span class='column3'>/</span>  
<span class='column4'>|</span> <span class='column2'>|</span> <span class='column3'>|</span><span class='column3'>/</span><span class='column1'>|</span>   </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=64925b4e8f7890f5447d9655b2c69dd59a93f7cd'>Improve $specrule interface</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 22:57:10 +0200'>2019-04-23</span></td><td>2</td><td><span class='deletions'>-9</span>/<span class='insertions'>+19</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=4575e4ad86494e99dd05200f7242dfa632053c78'>Improve $specrule interface</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 22:18:04 +0200'>2019-04-23</span></td><td>1</td><td><span class='deletions'>-20</span>/<span class='insertions'>+18</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=71c38d9de527e1a8b55ba295df459fbcf2a0fe47'>Add $specrule cells for $setup/$hold/$skew specify rules</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 21:36:59 +0200'>2019-04-23</span></td><td>2</td><td><span class='deletions'>-2</span>/<span class='insertions'>+78</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=e807e88b607834170692f56a5538b89fd4175a36'>Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 21:36:59 +0200'>2019-04-23</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
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<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
nomenclature

Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=41b843c27b486ef4b3c0044fbb00b161faaf89d9'>Un-break default specify parser</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 21:36:59 +0200'>2019-04-23</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=3cc95fb4be27a3e130563db102ed268876027288'>Add specify parser</a></td><td>Clifford Wolf</td><td><span title='2019-04-23 21:36:59 +0200'>2019-04-23</span></td><td>4</td><td><span class='deletions'>-33</span>/<span class='insertions'>+243</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=a98069d76284ac31fd6652236ab40ecc3f584816'>verilog_parser: Fix Bison warning</a></td><td>Ben Widawsky</td><td><span title='2019-05-05 19:36:27 -0700'>2019-05-05</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column1'>|</span> <span class='column3'>|</span><span class='column1'>_</span><span class='column3'>|</span><span class='column1'>/</span>  
<span class='column1'>|</span><span class='column1'>/</span><span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column1'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   </td>
<td colspan='5' class='logmsg'>
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> <span class='column3'>|</span>   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=70d0f389ad6e7e0ad762b62d3a626a4db5b23827'>Merge pull request #988 from YosysHQ/clifford/fix987</a></td><td>Clifford Wolf</td><td><span title='2019-05-04 21:58:25 +0200'>2019-05-04</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span><span class='column5'>\</span> <span class='column3'>\</span> <span class='column3'>\</span>  
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> 
<span class='column4'>|</span> <span class='column5'>|</span> <span class='column3'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
Add approximate support for SV "var" keyword

</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column3'>|</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=9804c86e87ec83edd29d224f01311b6ae1d41181'>Add approximate support for SV "var" keyword, fixes #987</a></td><td>Clifford Wolf</td><td><span title='2019-05-04 07:52:51 +0200'>2019-05-04</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span><span class='column3'>/</span>  
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<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column4'>|</span> <span class='column3'>|</span> <span class='column3'>|</span>   </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>/</span> <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=66d6ca2de2e31d7c0460ae314b61136e42ded8c5'>Add support for SVA "final" keyword</a></td><td>Clifford Wolf</td><td><span title='2019-05-04 09:25:32 +0200'>2019-05-04</span></td><td>2</td><td><span class='deletions'>-1</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column3'>|</span><span class='column3'>/</span> <span class='column3'>/</span>  
<span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column3'>|</span> <span class='column3'>|</span>   
<span class='column3'>|</span> <span class='column3'>|</span>   </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column3'>/</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=84f3a796e1232b19674a412b5d011d208d923f5c'>Include filename in "Executing Verilog-2005 frontend" message, fixes #959</a></td><td>Clifford Wolf</td><td><span title='2019-04-30 15:37:46 +0200'>2019-04-30</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column3'>|</span><span class='column3'>/</span>  
<span class='column3'>|</span>   
<span class='column3'>|</span>   
<span class='column3'>|</span>   </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/frontends/verilog?id=fb7f02be5561ccfd5bee5f3235fbbae5ef618f36'>New behavior for front-end handling of whiteboxes</a></td><td>Clifford Wolf</td><td><span title='2019-04-20 22:24:50 +0200'>2019-04-20</span></td><td>3</td><td><span class='deletions'>-16</span>/<span class='insertions'>+30</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
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ses can be performed best at the RTL level. Examples include FSM
detection and optimization, identification of memories or other larger building blocks
and identification of shareable resources.

Note that RTL is the first abstraction level in which the circuit is represented as a
graph of circuit elements (registers and combinatorial cells) and signals. Such a graph,
when encoded as list of cells and connections, is called a netlist.

RTL synthesis is easy as each circuit node element in the netlist can simply be replaced
with an equivalent gate-level circuit. However, usually the term <span class="nb">{</span><span class="k">\it</span> RTL synthesis<span class="nb">}</span> does
not only refer to synthesizing an RTL netlist to a gate level netlist but also to performing
a number of highly sophisticated optimizations within the RTL representation, such as
the examples listed above.

A number of FOSS tools exist that can perform isolated tasks within the domain of RTL
synthesis steps. But there seems to be no FOSS tool that covers a wide range of RTL
synthesis operations.

<span class="k">\subsection</span><span class="nb">{</span>Logical Gate Level<span class="nb">}</span>

At the logical gate level the design is represented by a netlist that uses only
cells from a small number of single-bit cells, such as basic logic gates (AND,
OR, NOT, XOR, etc.) and registers (usually D-Type Flip-flops).

A number of netlist formats exists that can be used on this level, e.g.~the Electronic Design
Interchange Format (EDIF), but for ease of simulation often a HDL netlist is used. The latter
is a HDL file (Verilog or VHDL) that only uses the most basic language constructs for instantiation
and connecting of cells.

There are two challenges in logic synthesis: First finding opportunities for optimizations
within the gate level netlist and second the optimal (or at least good) mapping of the logic
gate netlist to an equivalent netlist of physically available gate types.

The simplest approach to logic synthesis is <span class="nb">{</span><span class="k">\it</span> two-level logic synthesis<span class="nb">}</span>, where a logic function
is converted into a sum-of-products representation, e.g.~using a Karnaugh map.
This is a simple approach, but has exponential worst-case effort and cannot make efficient use of
physical gates other than AND/NAND-, OR/NOR- and NOT-Gates.

Therefore modern logic synthesis tools utilize much more complicated <span class="nb">{</span><span class="k">\it</span> multi-level logic
synthesis<span class="nb">}</span> algorithms <span class="k">\cite</span><span class="nb">{</span>MultiLevelLogicSynth<span class="nb">}</span>. Most of these algorithms convert the
logic function to a Binary-Decision-Diagram (BDD) or And-Inverter-Graph (AIG) and work from that
representation. The former has the advantage that it has a unique normalized form. The latter has
much better worst case performance and is therefore better suited for the synthesis of large
logic functions.

Good FOSS tools exists for multi-level logic synthesis <span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span>
<span class="k">\citeweblink</span><span class="nb">{</span>AIGER<span class="nb">}</span> <span class="k">\citeweblink</span><span class="nb">{</span>MVSIS<span class="nb">}</span>.

Yosys contains basic logic synthesis functionality but can also use ABC
<span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span> for the logic synthesis step. Using ABC is recommended.

<span class="k">\subsection</span><span class="nb">{</span>Physical Gate Level<span class="nb">}</span>

On the physical gate level only gates are used that are physically available on
the target architecture. In some cases this may only be NAND, NOR and NOT gates as well as
D-Type registers. In other cases this might include cells that are more complex than the cells
used at the logical gate level (e.g.~complete half-adders). In the case of an FPGA-based
design the physical gate level representation is a netlist of LUTs with optional output
registers, as these are the basic building blocks of FPGA logic cells.

For the synthesis tool chain this abstraction is usually the lowest level. In
case of an ASIC-based design the cell library might contain further information on
how the physical cells map to individual switches (transistors).

<span class="k">\subsection</span><span class="nb">{</span>Switch Level<span class="nb">}</span>

A switch level representation of a circuit is a netlist utilizing single transistors as cells.
Switch level modelling is possible in Verilog and VHDL, but is seldom used in modern designs,
as in modern digital ASIC or FPGA flows the physical gates are considered the atomic build blocks
of the logic circuit.

<span class="k">\subsection</span><span class="nb">{</span>Yosys<span class="nb">}</span>

Yosys is a Verilog HDL synthesis tool. This means that it takes a behavioural
design description as input and generates an RTL, logical gate or physical gate
level description of the design as output.  Yosys&#39; main strengths are behavioural
and RTL synthesis. A wide range of commands (synthesis passes) exist
within Yosys that can be used to perform a wide range of synthesis tasks within
the domain of behavioural, rtl and logic synthesis. Yosys is designed to be
extensible and therefore is a good basis for implementing custom synthesis
tools for specialised tasks.

<span class="k">\section</span><span class="nb">{</span>Features of Synthesizable Verilog<span class="nb">}</span>

The subset of Verilog <span class="k">\cite</span><span class="nb">{</span>Verilog2005<span class="nb">}</span> that is synthesizable is specified in
a separate IEEE standards document, the IEEE standard 1364.1-2002 <span class="k">\cite</span><span class="nb">{</span>VerilogSynth<span class="nb">}</span>.
This standard also describes how certain language constructs are to be interpreted in
the scope of synthesis.

This section provides a quick overview of the most important features of
synthesizable Verilog, structured in order of increasing complexity.

<span class="k">\subsection</span><span class="nb">{</span>Structural Verilog<span class="nb">}</span>

<span class="nb">{</span><span class="k">\it</span> Structural Verilog<span class="nb">}</span> (also known as <span class="nb">{</span><span class="k">\it</span> Verilog Netlists<span class="nb">}</span>) is a Netlist in
Verilog syntax. Only the following language constructs are used in this case:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Constant values
<span class="k">\item</span> Wire and port declarations
<span class="k">\item</span> Static assignments of signals to other signals
<span class="k">\item</span> Cell instantiations
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Many tools (especially at the back end of the synthesis chain) only support
structural Verilog as input. ABC is an example of such a tool. Unfortunately
there is no standard specifying what <span class="nb">{</span><span class="k">\it</span> Structural Verilog<span class="nb">}</span> actually is,
leading to some confusion about what syntax constructs are supported in
structural Verilog when it comes to features such as attributes or multi-bit
signals.

<span class="k">\subsection</span><span class="nb">{</span>Expressions in Verilog<span class="nb">}</span>

In all situations where Verilog accepts a constant value or signal name,
expressions using arithmetic operations such as
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>+<span class="nb">}</span>, <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>-<span class="nb">}</span> and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>*<span class="nb">}</span>,
boolean operations such as
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{&amp;}</span> (AND), <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>|<span class="nb">}</span> (OR) and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{^}</span> (XOR)
and many others (comparison operations, unary operator, etc.) can also be used.

During synthesis these operators are replaced by cells that implement the respective function.

Many FOSS tools that claim to be able to process Verilog in fact only support
basic structural Verilog and simple expressions. Yosys can be used to convert
full featured synthesizable Verilog to this simpler subset, thus enabling such
applications to be used with a richer set of Verilog features.

<span class="k">\subsection</span><span class="nb">{</span>Behavioural Modelling<span class="nb">}</span>

Code that utilizes the Verilog <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span> statement is using <span class="nb">{</span><span class="k">\it</span> Behavioural
Modelling<span class="nb">}</span>. In behavioural modelling, a circuit is described by means of imperative
program code that is executed on certain events, namely any change, a rising
edge, or a falling edge of a signal. This is a very flexible construct during
simulation but is only synthesizable when one of the following is modelled:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Asynchronous or latched logic<span class="nb">}</span> <span class="k">\\</span>
In this case the sensitivity list must contain all expressions that are used within
the <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span> block. The syntax <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>@*<span class="nb">}</span> can be used
for these cases. Examples of this kind include:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
// asynchronous
always @* begin
	if (add<span class="nb">_</span>mode)
		y &lt;= a + b;
	else
		y &lt;= a - b;
end

// latched
always @* begin
	if (!hold)
		y &lt;= a + b;
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

Note that latched logic is often considered bad style and in many cases just
the result of sloppy HDL design. Therefore many synthesis tools generate warnings
whenever latched logic is generated.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Synchronous logic (with optional synchronous reset)<span class="nb">}</span> <span class="k">\\</span>
This is logic with d-type flip-flops on the output. In this case the sensitivity
list must only contain the respective clock edge. Example:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
// counter with synchronous reset
always @(posedge clk) begin
	if (reset)
		y &lt;= 0;
	else
		y &lt;= y + 1;
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Synchronous logic with asynchronous reset<span class="nb">}</span> <span class="k">\\</span>
This is logic with d-type flip-flops with asynchronous resets on the output. In
this case the sensitivity list must only contain the respective clock and reset edges.
The values assigned in the reset branch must be constant. Example:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
// counter with asynchronous reset
always @(posedge clk, posedge reset) begin
	if (reset)
		y &lt;= 0;
	else
		y &lt;= y + 1;
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Many synthesis tools support a wider subset of flip-flops that can be modelled
using <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span>-statements (including Yosys). But only the ones listed above
are covered by the Verilog synthesis standard and when writing new designs one
should limit herself or himself to these cases.

In behavioural modelling, blocking assignments (=) and non-blocking assignments
(&lt;=) can be used. The concept of blocking vs.~non-blocking assignment is one
of the most misunderstood constructs in Verilog <span class="k">\cite</span><span class="nb">{</span>Cummings00<span class="nb">}</span>.

The blocking assignment behaves exactly like an assignment in any imperative
programming language, while with the non-blocking assignment the right hand side
of the assignment is evaluated immediately but the actual update of the left
hand side register is delayed until the end of the time-step. For example the Verilog
code <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>a &lt;= b; b &lt;= a;<span class="nb">}</span> exchanges the values of
the two registers. See Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:blocking<span class="nb">_</span>nonblocking<span class="nb">}</span> for a more
detailed description of this behaviour.

<span class="k">\subsection</span><span class="nb">{</span>Functions and Tasks<span class="nb">}</span>

Verilog supports <span class="nb">{</span><span class="k">\it</span> Functions<span class="nb">}</span> and <span class="nb">{</span><span class="k">\it</span> Tasks<span class="nb">}</span> to bundle statements that are
used in multiple places (similar to <span class="nb">{</span><span class="k">\it</span> Procedures<span class="nb">}</span> in imperative programming).
Both constructs can be implemented easily by substituting the function/task-call
with the body of the function or task.

<span class="k">\subsection</span><span class="nb">{</span>Conditionals, Loops and Generate-Statements<span class="nb">}</span>

Verilog supports <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>if-else<span class="nb">}</span>-statements and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>for<span class="nb">}</span>-loops inside <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>always<span class="nb">}</span>-statements.

It also supports both features in <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>generate<span class="nb">}</span>-statements
on the module level. This can be used to selectively enable or disable parts of the
module based on the module parameters (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>if-else<span class="nb">}</span>)
or to generate a set of similar subcircuits (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>for<span class="nb">}</span>).

While the <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>if-else<span class="nb">}</span>-statement
inside an always-block is part of behavioural modelling, the three other cases
are (at least for a synthesis tool) part of a built-in macro processor. Therefore it must
be possible for the synthesis tool to completely unroll all loops and evaluate the
condition in all <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>if-else<span class="nb">}</span>-statement in
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>generate<span class="nb">}</span>-statements using const-folding.

Examples for this can be found in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>for<span class="nb">}</span> and
Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>gen<span class="nb">}</span> in App.~<span class="k">\ref</span><span class="nb">{</span>chapter:sota<span class="nb">}</span>.

<span class="k">\subsection</span><span class="nb">{</span>Arrays and Memories<span class="nb">}</span>

Verilog supports arrays. This is in general a synthesizable language feature.
In most cases arrays can be synthesized by generating addressable memories.
However, when complex or asynchronous access patterns are used, it is not
possible to model an array as memory. In these cases the array must
be modelled using individual signals for each word and all accesses to the array
must be implemented using large multiplexers.

In some cases it would be possible to model an array using memories, but it
is not desired. Consider the following delay circuit:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
module (clk, in<span class="nb">_</span>data, out<span class="nb">_</span>data);

parameter BITS = 8;
parameter STAGES = 4;

input clk;
input [BITS-1:0] in<span class="nb">_</span>data;
output [BITS-1:0] out<span class="nb">_</span>data;
reg [BITS-1:0] ffs [STAGES-1:0];

integer i;
always @(posedge clk) begin
	ffs[0] &lt;= in<span class="nb">_</span>data;
	for (i = 1; i &lt; STAGES; i = i+1)
		ffs[i] &lt;= ffs[i-1];
end

assign out<span class="nb">_</span>data = ffs[STAGES-1];

endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

This could be implemented using an addressable memory with <span class="nb">{</span><span class="k">\tt</span> STAGES<span class="nb">}</span> input
and output ports. A better implementation would be to use a simple chain of flip-flops
(a so-called shift register).
This better implementation can either be obtained by first creating a memory-based
implementation and then optimizing it based on the static address signals for all ports
or directly identifying such situations in the language front end and converting
all memory accesses to direct accesses to the correct signals.

<span class="k">\section</span><span class="nb">{</span>Challenges in Digital Circuit Synthesis<span class="nb">}</span>

This section summarizes the most important challenges in digital circuit
synthesis. Tools can be characterized by how well they address these topics.

<span class="k">\subsection</span><span class="nb">{</span>Standards Compliance<span class="nb">}</span>

The most important challenge is compliance with the HDL standards in question (in case
of Verilog the IEEE Standards 1364.1-2002 and 1364-2005). This can be broken down in two
items:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Completeness of implementation of the standard
<span class="k">\item</span> Correctness of implementation of the standard
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Completeness is mostly important to guarantee compatibility
with existing HDL code. Once a design has been verified and tested, HDL designers
are very reluctant regarding changes to the design, even if it is only about
a few minor changes to work around a missing feature in a new synthesis tool.

Correctness is crucial. In some areas this is obvious (such as
correct synthesis of basic behavioural models). But it is also crucial for the
areas that concern minor details of the standard, such as the exact rules
for handling signed expressions, even when the HDL code does not target
different synthesis tools. This is because (unlike software source code that
is only processed by compilers), in most design flows HDL code is not only
processed by the synthesis tool but also by one or more simulators and sometimes
even a formal verification tool. It is key for this verification process
that all these tools use the same interpretation for the HDL code.

<span class="k">\subsection</span><span class="nb">{</span>Optimizations<span class="nb">}</span>

Generally it is hard to give a one-dimensional description of how well a synthesis tool
optimizes the design. First of all because not all optimizations are applicable to all
designs and all synthesis tasks. Some optimizations work (best) on a coarse-grained level
(with complex cells such as adders or multipliers) and others work (best) on a fine-grained
level (single bit gates). Some optimizations target area and others target speed.
Some work well on large designs while others don&#39;t scale well and can only be applied
to small designs.

A good tool is capable of applying a wide range of optimizations at different
levels of abstraction and gives the designer control over which optimizations
are performed (or skipped) and what the optimization goals are.

<span class="k">\subsection</span><span class="nb">{</span>Technology Mapping<span class="nb">}</span>

Technology mapping is the process of converting the design into a netlist of
cells that are available in the target architecture. In an ASIC flow this might
be the process-specific cell library provided by the fab. In an FPGA flow this
might be LUT cells as well as special function units such as dedicated multipliers.
In a coarse-grain flow this might even be more complex special function units.

An open and vendor independent tool is especially of interest if it supports
a wide range of different types of target architectures.

<span class="k">\section</span><span class="nb">{</span>Script-Based Synthesis Flows<span class="nb">}</span>

A digital design is usually started by implementing a high-level or
system-level simulation of the desired function. This description is then
manually transformed (or re-implemented) into a synthesizable lower-level
description (usually at the behavioural level) and the equivalence of the
two representations is verified by simulating both and comparing the simulation
results.

Then the synthesizable description is transformed to lower-level
representations using a series of tools and the results are again verified
using simulation. This process is illustrated in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>flow<span class="nb">}</span>.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t!]
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
			<span class="k">\tikzstyle</span><span class="nb">{</span>manual<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=8em, node distance=10em]
			<span class="k">\tikzstyle</span><span class="nb">{</span>auto<span class="nb">}</span> = [draw, fill=orange!10, rectangle, minimum height=2em, minimum width=8em, node distance=10em]

			<span class="k">\node</span><span class="na">[manual]</span> (sys) <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>8em<span class="nb">}</span>
				<span class="k">\center</span>
				System Level <span class="k">\\</span>
				Model
			<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;
			<span class="k">\node</span><span class="na">[manual]</span> (beh) [right of=sys] <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>8em<span class="nb">}</span>
				<span class="k">\center</span>
				Behavioral <span class="k">\\</span>
				Model
			<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;
			<span class="k">\node</span><span class="na">[auto]</span> (rtl) [right of=beh] <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>8em<span class="nb">}</span>
				<span class="k">\center</span>
				RTL <span class="k">\\</span>
				Model
			<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;
			<span class="k">\node</span><span class="na">[auto]</span> (gates) [right of=rtl] <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>8em<span class="nb">}</span>
				<span class="k">\center</span>
				Gate-Level <span class="k">\\</span>
				Model
			<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;

			<span class="k">\draw</span><span class="na">[-latex]</span> (beh) edge[double, bend left] node[above] <span class="nb">{</span>synthesis<span class="nb">}</span> (rtl);
			<span class="k">\draw</span><span class="na">[-latex]</span> (rtl) edge[double, bend left] node[above] <span class="nb">{</span>synthesis<span class="nb">}</span> (gates);

			<span class="k">\draw</span><span class="na">[latex-latex]</span> (sys) edge[bend right] node[below] <span class="nb">{</span>verify<span class="nb">}</span> (beh);
			<span class="k">\draw</span><span class="na">[latex-latex]</span> (beh) edge[bend right] node[below] <span class="nb">{</span>verify<span class="nb">}</span> (rtl);
			<span class="k">\draw</span><span class="na">[latex-latex]</span> (rtl) edge[bend right] node[below] <span class="nb">{</span>verify<span class="nb">}</span> (gates);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Typical design flow. Green boxes represent manually created models. Orange boxes represent
	models generated by synthesis tools.<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>flow<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

In this example the System Level Model and the Behavioural Model are both
manually written design files. After the equivalence of system level model
and behavioural model has been verified, the lower level representations of the
design can be generated using synthesis tools. Finally the RTL Model and
the Gate-Level Model are verified and the design process is finished.

However, in any real-world design effort there will be multiple iterations for
this design process. The reason for this can be the late change of a design
requirement or the fact that the analysis of a low-abstraction model (e.g.~gate-level
timing analysis) revealed that a design change is required in order to meet
the design requirements (e.g.~maximum possible clock speed).

Whenever the behavioural model or the system level model is
changed their equivalence must be re-verified by re-running the simulations
and comparing the results. Whenever the behavioural model is changed the
synthesis must be re-run and the synthesis results must be re-verified.

In order to guarantee reproducibility it is important to be able to re-run all
automatic steps in a design project with a fixed set of settings easily.
Because of this, usually all programs used in a synthesis flow can be
controlled using scripts. This means that all functions are available via
text commands. When such a tool provides a GUI, this is complementary to,
and not instead of, a command line interface.

Usually a synthesis flow in an UNIX/Linux environment would be controlled by a
shell script that calls all required tools (synthesis and simulation/verification
in this example) in the correct order. Each of these tools would be called with
a script file containing commands for the respective tool. All settings required
for the tool would be provided by these script files so that no manual interaction
would be necessary. These script files are considered design sources and should
be kept under version control just like the source code of the system level and the
behavioural model.

<span class="k">\section</span><span class="nb">{</span>Methods from Compiler Design<span class="nb">}</span>

Some parts of synthesis tools involve problem domains that are traditionally known from
compiler design. This section addresses some of these domains.

<span class="k">\subsection</span><span class="nb">{</span>Lexing and Parsing<span class="nb">}</span>

The best known concepts from compiler design are probably <span class="nb">{</span><span class="k">\it</span> lexing<span class="nb">}</span> and <span class="nb">{</span><span class="k">\it</span> parsing<span class="nb">}</span>.
These are two methods that together can be used to process complex computer languages
easily. <span class="k">\cite</span><span class="nb">{</span>Dragonbook<span class="nb">}</span>

A <span class="nb">{</span><span class="k">\it</span> lexer<span class="nb">}</span> consumes single characters from the input and generates a stream of <span class="nb">{</span><span class="k">\it</span> lexical
tokens<span class="nb">}</span> that consist of a <span class="nb">{</span><span class="k">\it</span> type<span class="nb">}</span> and a <span class="nb">{</span><span class="k">\it</span> value<span class="nb">}</span>. For example the Verilog input
``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>assign foo = bar + 42;<span class="nb">}</span>&#39;&#39; might be translated by the lexer
to the list of lexical tokens given in Tab.~<span class="k">\ref</span><span class="nb">{</span>tab:Basics<span class="nb">_</span>tokens<span class="nb">}</span>.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>ll<span class="nb">}</span>
Token-Type <span class="nb">&amp;</span> Token-Value <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>ASSIGN <span class="nb">&amp;</span> - <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>IDENTIFIER <span class="nb">&amp;</span> ``<span class="nb">{</span><span class="k">\tt</span> foo<span class="nb">}</span>&#39;&#39; <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>EQ <span class="nb">&amp;</span> - <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>IDENTIFIER <span class="nb">&amp;</span> ``<span class="nb">{</span><span class="k">\tt</span> bar<span class="nb">}</span>&#39;&#39; <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>PLUS <span class="nb">&amp;</span> - <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>NUMBER <span class="nb">&amp;</span> 42 <span class="k">\\</span>
<span class="k">\tt</span> TOK<span class="k">\_</span>SEMICOLON <span class="nb">&amp;</span> - <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Exemplary token list for the statement ``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>assign foo = bar + 42;<span class="nb">}</span>&#39;&#39;.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:Basics<span class="nb">_</span>tokens<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

The lexer is usually generated by a lexer generator (e.g.~<span class="nb">{</span><span class="k">\tt</span> flex<span class="nb">}</span> <span class="k">\citeweblink</span><span class="nb">{</span>flex<span class="nb">}</span>) from a
description file that is using regular expressions to specify the text pattern that should match
the individual tokens.

The lexer is also responsible for skipping ignored characters (such as whitespace outside string
constants and comments in the case of Verilog) and converting the original text snippet to a token
value.

Note that individual keywords use different token types (instead of a keyword type with different
token values). This is because the parser usually can only use the Token-Type to make a decision on
the grammatical role of a token.

The parser then transforms the list of tokens into a parse tree that closely resembles the productions
from the computer languages grammar. As the lexer, the parser is also typically generated by a code
generator (e.g.~<span class="nb">{</span><span class="k">\tt</span> bison<span class="nb">}</span> <span class="k">\citeweblink</span><span class="nb">{</span>bison<span class="nb">}</span>) from a grammar description in Backus-Naur Form (BNF).

Let&#39;s consider the following BNF (in Bison syntax):

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
assign<span class="nb">_</span>stmt: TOK<span class="nb">_</span>ASSIGN TOK<span class="nb">_</span>IDENTIFIER TOK<span class="nb">_</span>EQ expr TOK<span class="nb">_</span>SEMICOLON;
expr: TOK<span class="nb">_</span>IDENTIFIER | TOK<span class="nb">_</span>NUMBER | expr TOK<span class="nb">_</span>PLUS expr;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[b!]
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
			<span class="k">\tikzstyle</span><span class="nb">{</span>node<span class="nb">}</span> = [draw, fill=green!10, ellipse, minimum height=2em, minimum width=8em, node distance=10em]

			<span class="k">\draw</span> (+0,+1) node[node] (n1) <span class="nb">{</span><span class="k">\tt</span> assign<span class="k">\_</span>stmt<span class="nb">}</span>;

			<span class="k">\draw</span> (-6,-1) node[node] (n11) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>ASSIGN<span class="nb">}</span>;
			<span class="k">\draw</span> (-3,-2) node[node] (n12) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>IDENTIFIER<span class="nb">}</span>;
			<span class="k">\draw</span> (+0,-1) node[node] (n13) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>EQ<span class="nb">}</span>;
			<span class="k">\draw</span> (+3,-2) node[node] (n14) <span class="nb">{</span><span class="k">\tt</span> expr<span class="nb">}</span>;
			<span class="k">\draw</span> (+6,-1) node[node] (n15) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>SEMICOLON<span class="nb">}</span>;

			<span class="k">\draw</span> (-1,-4) node[node] (n141) <span class="nb">{</span><span class="k">\tt</span> expr<span class="nb">}</span>;
			<span class="k">\draw</span> (+3,-4) node[node] (n142) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>PLUS<span class="nb">}</span>;
			<span class="k">\draw</span> (+7,-4) node[node] (n143) <span class="nb">{</span><span class="k">\tt</span> expr<span class="nb">}</span>;

			<span class="k">\draw</span> (-1,-5.5) node[node] (n1411) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>IDENTIFIER<span class="nb">}</span>;
			<span class="k">\draw</span> (+7,-5.5) node[node] (n1431) <span class="nb">{</span><span class="k">\tt</span> TOK<span class="k">\_</span>NUMBER<span class="nb">}</span>;

			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n11);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n12);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n13);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n14);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n15);

			<span class="k">\draw</span><span class="na">[-latex]</span> (n14) -- (n141);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n14) -- (n142);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n14) -- (n143);

			<span class="k">\draw</span><span class="na">[-latex]</span> (n141) -- (n1411);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n143) -- (n1431);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Example parse tree for the Verilog expression ``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>assign foo = bar + 42;<span class="nb">}</span>&#39;&#39;.<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>parsetree<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

The parser converts the token list to the parse tree in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>parsetree<span class="nb">}</span>. Note that the parse
tree never actually exists as a whole as data structure in memory. Instead the parser calls user-specified
code snippets (so-called <span class="nb">{</span><span class="k">\it</span> reduce-functions<span class="nb">}</span>) for all inner nodes of the parse tree in depth-first order.

In some very simple applications (e.g.~code generation for stack machines) it is possible to perform the
task at hand directly in the reduce functions. But usually the reduce functions are only used to build an in-memory
data structure with the relevant information from the parse tree. This data structure is called an <span class="nb">{</span><span class="k">\it</span> abstract
syntax tree<span class="nb">}</span> (AST).

The exact format for the abstract syntax tree is application specific (while the format of the parse tree and token
list are mostly dictated by the grammar of the language at hand). Figure~<span class="k">\ref</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>ast<span class="nb">}</span> illustrates what an
AST for the parse tree in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>parsetree<span class="nb">}</span> could look like.

Usually the AST is then converted into yet another representation that is more suitable for further processing.
In compilers this is often an assembler-like three-address-code intermediate representation. <span class="k">\cite</span><span class="nb">{</span>Dragonbook<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t]
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
			<span class="k">\tikzstyle</span><span class="nb">{</span>node<span class="nb">}</span> = [draw, fill=green!10, ellipse, minimum height=2em, minimum width=8em, node distance=10em]

			<span class="k">\draw</span> (+0,+0) node[node] (n1) <span class="nb">{</span><span class="k">\tt</span> ASSIGN<span class="nb">}</span>;

			<span class="k">\draw</span> (-2,-2) node[node] (n11) <span class="nb">{</span><span class="k">\tt</span> ID: foo<span class="nb">}</span>;
			<span class="k">\draw</span> (+2,-2) node[node] (n12) <span class="nb">{</span><span class="k">\tt</span> PLUS<span class="nb">}</span>;

			<span class="k">\draw</span> (+0,-4) node[node] (n121) <span class="nb">{</span><span class="k">\tt</span> ID: bar<span class="nb">}</span>;
			<span class="k">\draw</span> (+4,-4) node[node] (n122) <span class="nb">{</span><span class="k">\tt</span> CONST: 42<span class="nb">}</span>;

			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n11);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n12);

			<span class="k">\draw</span><span class="na">[-latex]</span> (n12) -- (n121);
			<span class="k">\draw</span><span class="na">[-latex]</span> (n12) -- (n122);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Example abstract syntax tree for the Verilog expression ``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>assign foo = bar + 42;<span class="nb">}</span>&#39;&#39;.<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:Basics<span class="nb">_</span>ast<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Multi-Pass Compilation<span class="nb">}</span>

Complex problems are often best solved when split up into smaller problems. This is certainly true
for compilers as well as for synthesis tools. The components responsible for solving the smaller problems can
be connected in two different ways: through <span class="nb">{</span><span class="k">\it</span> Single-Pass Pipelining<span class="nb">}</span> and by using <span class="nb">{</span><span class="k">\it</span> Multiple Passes<span class="nb">}</span>.

Traditionally a parser and lexer are connected using the pipelined approach: The lexer provides a function that
is called by the parser. This function reads data from the input until a complete lexical token has been read. Then
this token is returned to the parser. So the lexer does not first generate a complete list of lexical tokens
and then pass it to the parser. Instead they run concurrently and the parser can consume tokens as
the lexer produces them.

The single-pass pipelining approach has the advantage of lower memory footprint (at no time must the complete design
be kept in memory) but has the disadvantage of tighter coupling between the interacting components.

Therefore single-pass pipelining should only be used when the lower memory footprint is required or the
components are also conceptually tightly coupled. The latter certainly is the case for a parser and its lexer.
But when data is passed between two conceptually loosely coupled components it is often
beneficial to use a multi-pass approach.

In the multi-pass approach the first component processes all the data and the result is stored in a in-memory
data structure. Then the second component is called with this data. This reduces complexity, as only one
component is running at a time. It also improves flexibility as components can be exchanged easier.

Most modern compilers are multi-pass compilers.

<span class="k">\iffalse</span>
<span class="k">\subsection</span><span class="nb">{</span>Static Single Assignment Form<span class="nb">}</span>

In imperative programming (and behavioural HDL design) it is possible to assign the same variable multiple times.
This can either mean that the variable is independently used in two different contexts or that the final value
of the variable depends on a condition.

The following examples show C code in which one variable is used independently in two different contexts:

<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=C++]
void demo1()
<span class="nb">{</span>
	int a = 1;
	printf(&quot;<span class="c">%d\n&quot;, a);</span>

	a = 2;
	printf(&quot;<span class="c">%d\n&quot;, a);</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[frame=single,language=C++]
void demo1()
<span class="nb">{</span>
	int a = 1;
	printf(&quot;<span class="c">%d\n&quot;, a);</span>

	int b = 2;
	printf(&quot;<span class="c">%d\n&quot;, b);</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=C++]
void demo2(bool foo)
<span class="nb">{</span>
	int a;
	if (foo) <span class="nb">{</span>
		a = 23;
		printf(&quot;<span class="c">%d\n&quot;, a);</span>
	<span class="nb">}</span> else <span class="nb">{</span>
		a = 42;
		printf(&quot;<span class="c">%d\n&quot;, a);</span>
	<span class="nb">}</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[frame=single,language=C++]
void demo2(bool foo)
<span class="nb">{</span>
	int a, b;
	if (foo) <span class="nb">{</span>
		a = 23;
		printf(&quot;<span class="c">%d\n&quot;, a);</span>
	<span class="nb">}</span> else <span class="nb">{</span>
		b = 42;
		printf(&quot;<span class="c">%d\n&quot;, b);</span>
	<span class="nb">}</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>

In both examples the left version (only variable <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>a<span class="nb">}</span>) and the right version (variables
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>a<span class="nb">}</span> and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>b<span class="nb">}</span>) are equivalent. Therefore it is
desired for further processing to bring the code in an equivalent form for both cases.

In the following example the variable is assigned twice but it cannot be easily replaced by two variables:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[frame=single,language=C++]
void demo3(bool foo)
<span class="nb">{</span>
	int a = 23
	if (foo)
		a = 42;
	printf(&quot;<span class="c">%d\n&quot;, a);</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

Static single assignment (SSA) form is a representation of imperative code that uses identical representations
for the left and right version of demos 1 and 2, but can still represent demo 3. In SSA form each assignment
assigns a new variable (usually written with an index). But it also introduces a special <span class="s">$</span><span class="nv">\Phi</span><span class="s">$</span>-function to
merge the different instances of a variable when needed. In C-pseudo-code the demo 3 would be written as follows
using SSA from:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[frame=single,language=C++]
void demo3(bool foo)
<span class="nb">{</span>
	int a<span class="nb">_</span>1, a<span class="nb">_</span>2, a<span class="nb">_</span>3;
	a<span class="nb">_</span>1 = 23
	if (foo)
		a<span class="nb">_</span>2 = 42;
	a<span class="nb">_</span>3 = phi(a<span class="nb">_</span>1, a<span class="nb">_</span>2);
	printf(&quot;<span class="c">%d\n&quot;, a_3);</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The <span class="s">$</span><span class="nv">\Phi</span><span class="s">$</span>-function is usually interpreted as ``these variables must be stored
in the same memory location&#39;&#39; during code generation. Most modern compilers for imperative languages
such as C/C++ use SSA form for at least some of its passes as it is very easy to manipulate and analyse.
<span class="k">\fi</span>
</pre></div>
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