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Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
Eddie Hung
2019-06-27
1
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+18
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Add simcells.v, simlib.v, and some output
Eddie Hung
2019-06-27
1
-1
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+11
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tests: Check that Icarus can parse arch sim models
David Shah
2019-06-26
1
-0
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+8
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Merge pull request #1143 from YosysHQ/clifford/fix1135
Eddie Hung
2019-06-27
2
-5
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+26
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Add #1135 testcase
Eddie Hung
2019-06-27
2
-5
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+26
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Copy tests from eddie/fix1132
Eddie Hung
2019-06-27
1
-0
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+320
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Add testcase from #335, fixed by #1130
Eddie Hung
2019-06-25
1
-0
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+28
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Merge pull request #1130 from YosysHQ/eddie/fix710
Clifford Wolf
2019-06-25
2
-1
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+22
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Add test
Eddie Hung
2019-06-24
2
-1
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+22
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Merge remote-tracking branch 'origin/master' into eddie/muxpack
Eddie Hung
2019-06-22
5
-1
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+298
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Merge pull request #1108 from YosysHQ/clifford/fix1091
Eddie Hung
2019-06-21
1
-1
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+140
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Missing a `clean` and `opt_expr -mux_bool` in test
Eddie Hung
2019-06-20
1
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+4
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Add test
Eddie Hung
2019-06-20
1
-1
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+136
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Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
Eddie Hung
2019-06-21
2
-0
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+114
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Add shregmap -tech xilinx test
Eddie Hung
2019-06-12
2
-2
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+63
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Add test
Eddie Hung
2019-06-10
2
-0
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+53
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Merge pull request #1119 from YosysHQ/eddie/fix1118
Clifford Wolf
2019-06-21
1
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+11
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Add test
Eddie Hung
2019-06-20
1
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+11
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Extend sign extension tests
Eddie Hung
2019-06-20
1
-4
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+16
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Remove leftover comment
Eddie Hung
2019-06-20
1
-3
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+0
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Add test
Eddie Hung
2019-06-20
1
-0
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+24
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Add more tests
Eddie Hung
2019-06-21
2
-21
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+51
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Fix testcase
Eddie Hung
2019-06-21
1
-3
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+4
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Add more muxpack tests, with overlapping entries
Eddie Hung
2019-06-21
2
-1
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+84
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Merge branch 'master' into eddie/muxpack
Eddie Hung
2019-06-21
6
-21
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+62
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Update some .gitignore files
Clifford Wolf
2019-06-20
2
-3
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+3
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Add proper test for SV-style arrays
Clifford Wolf
2019-06-20
3
-6
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+16
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Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...
Clifford Wolf
2019-06-20
2
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+6
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Unpacked array declaration using size
Tobias Wölfel
2019-06-19
2
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+6
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Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Clifford Wolf
2019-06-19
2
-14
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+37
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Add defvalue test, minor autotest fixes for .sv files
Clifford Wolf
2019-06-19
2
-14
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+37
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Make tests/aiger less chatty
Clifford Wolf
2019-06-19
1
-4
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+6
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Merge remote-tracking branch 'origin/master' into eddie/muxpack
Eddie Hung
2019-06-10
1
-1
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+6
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Add some more comments
Eddie Hung
2019-06-10
1
-1
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+6
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Merge branch 'master' into eddie/muxpack
Eddie Hung
2019-06-07
28
-33
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+138
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Test *.aag too, by using *.aig as reference
Eddie Hung
2019-06-07
1
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+19
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Use ABC to convert from AIGER to Verilog
Eddie Hung
2019-06-07
1
-2
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+3
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Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung
2019-06-07
1
-21
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+15
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Add symbols to AIGER test inputs for ABC
Eddie Hung
2019-06-07
22
-8
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+40
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Merge pull request #1077 from YosysHQ/clifford/pr983
Clifford Wolf
2019-06-07
2
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+31
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Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
2
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+31
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Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
2
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+31
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Rename implicit_ports.sv test to implicit_ports.v
Clifford Wolf
2019-06-07
1
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+0
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Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
2
-12
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+1
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Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
4
-3
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+42
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SystemVerilog support for implicit named port connections
tux3
2019-06-06
4
-3
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+42
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Add nonexcl case test, comment out two others
Eddie Hung
2019-06-07
2
-22
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+57
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Add @cliffordwolf freduce testcase
Eddie Hung
2019-06-07
2
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+30
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Add nonexclusive test from @cliffordwolf
Eddie Hung
2019-06-07
2
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+28
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Another muxpack test
Eddie Hung
2019-06-07
2
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+32
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