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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 08:34:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 08:34:58 -0700 |
| commit | 0f6e914ef63d06ae77b54d246b61118c19647f26 (patch) | |
| tree | d4e8f6b0c1e46750ad3660a9b43550907746c32c /tests | |
| parent | 5c277c6325b78bfe18cf294b63ea69ff272e69c5 (diff) | |
| download | yosys-0f6e914ef63d06ae77b54d246b61118c19647f26.tar.gz yosys-0f6e914ef63d06ae77b54d246b61118c19647f26.tar.bz2 yosys-0f6e914ef63d06ae77b54d246b61118c19647f26.zip | |
Another muxpack test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/muxpack.v | 17 | ||||
| -rw-r--r-- | tests/various/muxpack.ys | 15 |
2 files changed, 32 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f1bd5ea8e..41dfed396 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -136,3 +136,20 @@ always @* else o <= i[7*W+:W]; endmodule + +module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s[0] == 1'b0) + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[0*W+:W]; + else + o <= i[1*W+:W]; + else + if (s[2] == 1'b0) + o <= i[2*W+:W]; + else + o <= i[3*W+:W]; + else + o <= i[4*W+:W]; +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 9ea743b9f..dd3c143d8 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -148,3 +148,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_bal_5_1 +prep +design -save gold +muxpack +opt +stat +select -assert-count 2 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |