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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-1256-37/+780
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| * Add some more commentsEddie Hung2019-06-101-1/+6
| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
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| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-072-0/+31
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| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
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| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-074-3/+42
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| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| * | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...Maciej Kurc2019-06-044-0/+46
| * | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
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| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
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| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| * | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| * | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| | * | Fix initEddie Hung2019-05-241-27/+27
| | * | Fix typosEddie Hung2019-05-241-6/+6
| | * | Add more testsEddie Hung2019-05-242-20/+41
| | * | Call procEddie Hung2019-05-241-1/+1
| | * | Fix duplicate driverEddie Hung2019-05-241-15/+15
| | * | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
| * | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
| * | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
| * | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
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| * | Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| * | Add test case from #997Clifford Wolf2019-05-071-0/+12
| * | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
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| | * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | * | More testingEddie Hung2019-05-032-2/+5
| | * | Fix spacingEddie Hung2019-05-031-6/+6
| | * | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
| * | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
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| | * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| | * | | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| * | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
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| | * | | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| * | | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
| * | | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
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| | * | | Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
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| * | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
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| | * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
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| * | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| * | | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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| * | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-012-0/+23
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* | Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-0/+38
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-224-0/+110
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