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* Proper example codeMiodrag Milanovic2022-03-142-1/+3
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
* Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-042-0/+15
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| * fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-182-0/+15
* | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
* | Added test casesMiodrag Milanovic2022-02-1638-0/+896
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+25
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-144-5/+51
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-112-0/+108
* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-0/+84
* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-077-0/+953
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| * bug fix and cleanupsMiodrag Milanovic2022-02-041-2/+2
| * Add test cases for co-simulationMiodrag Milanovic2022-02-027-0/+953
* | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-302-0/+208
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-192-1/+14
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| * anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
* | sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
* | sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
* | logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
* | fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
* | fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
* | sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
* | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-0/+34
* | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
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* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* sta: very crude static timing analysis passLofty2021-11-251-0/+81
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-279-73/+46
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-0/+79
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-0/+12
* Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-0/+21
* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-5/+7
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2440-79/+79
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| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
* | sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
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* abc9: make re-entrant (#2993)Eddie Hung2021-09-091-0/+20
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-0/+14
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