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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-10-21 02:58:10 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-10-21 04:10:01 +0200 |
| commit | e64456f92025c26f8b66e77901f78eca726d856a (patch) | |
| tree | f5ef1e534981a0267da5b1242daac39ff0fddd3e /tests | |
| parent | a0e9d9fef9af0ed83fd0d4aa2622d056674bf164 (diff) | |
| download | yosys-e64456f92025c26f8b66e77901f78eca726d856a.tar.gz yosys-e64456f92025c26f8b66e77901f78eca726d856a.tar.bz2 yosys-e64456f92025c26f8b66e77901f78eca726d856a.zip | |
extract_reduce: Refactor and fix input signal construction.
Fixes #3047.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug3047.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/opt/bug3047.ys b/tests/opt/bug3047.ys new file mode 100644 index 000000000..6713877ce --- /dev/null +++ b/tests/opt/bug3047.ys @@ -0,0 +1,12 @@ +read_verilog << EOT + +module test (A, B, C, D, Y); + input A, B, C, D; + output Y; + assign Y = A^B^C^D^A; +endmodule + +EOT + +techmap +equiv_opt -assert extract_reduce |