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| * | | | | | | | | | | | | | | | | | | | | | | | | | Add #1135 testcaseEddie Hung2019-06-272-5/+26
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* / / / / / / / / / / / / / / / / / / / / / / / / / Copy tests from eddie/fix1132Eddie Hung2019-06-271-0/+320
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* | | | | | | | | | | | | | | | | | | | | | | | | Add testcase from #335, fixed by #1130Eddie Hung2019-06-251-0/+28
* | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1130 from YosysHQ/eddie/fix710Clifford Wolf2019-06-252-1/+22
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| * | | | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-06-242-1/+22
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* | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-225-1/+298
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| * | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1108 from YosysHQ/clifford/fix1091Eddie Hung2019-06-211-1/+140
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| | * | | | | | | | | | | | | | | | | | | | | | | | Missing a `clean` and `opt_expr -mux_bool` in testEddie Hung2019-06-201-0/+4
| | * | | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-06-201-1/+136
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| * | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-212-0/+114
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| | * | | | | | | | | | | | | | | | | | | | | | | | Add shregmap -tech xilinx testEddie Hung2019-06-122-2/+63
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| | * | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-06-102-0/+53
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| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+11
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| | * | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-06-201-0/+11
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| * | | | | | | | | | | | | | | | | | | | | | | Extend sign extension testsEddie Hung2019-06-201-4/+16
| * | | | | | | | | | | | | | | | | | | | | | | Remove leftover commentEddie Hung2019-06-201-3/+0
| * | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-06-201-0/+24
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* | | | | | | | | | | | | | | | | | | | | | | Add more testsEddie Hung2019-06-212-21/+51
* | | | | | | | | | | | | | | | | | | | | | | Fix testcaseEddie Hung2019-06-211-3/+4
* | | | | | | | | | | | | | | | | | | | | | | Add more muxpack tests, with overlapping entriesEddie Hung2019-06-212-1/+84
* | | | | | | | | | | | | | | | | | | | | | | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-216-21/+62
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| * | | | | | | | | | | | | | | | | | | | | | Update some .gitignore filesClifford Wolf2019-06-202-3/+3
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| * | | | | | | | | | | | | | | | | | | | | Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| * | | | | | | | | | | | | | | | | | | | | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-202-0/+6
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| | * | | | | | | | | | | | | | | | | | | | | Unpacked array declaration using sizeTobias Wölfel2019-06-192-0/+6
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| * | | | | | | | | | | | | | | | | | | | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-192-14/+37
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| | * | | | | | | | | | | | | | | | | | | | | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
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| * / / / / / / / / / / / / / / / / / / / / Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
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* | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-101-1/+6
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| * | | | | | | | | | | | | | | | | | | | Add some more commentsEddie Hung2019-06-101-1/+6
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* | | | | | | | | | | | | | | | | | | | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-0728-33/+138
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| * | | | | | | | | | | | | | | | | | | Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| * | | | | | | | | | | | | | | | | | | Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| * | | | | | | | | | | | | | | | | | | Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| * | | | | | | | | | | | | | | | | | | Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
| * | | | | | | | | | | | | | | | | | | Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-072-0/+31
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| | | * | | | | | | | | | | | | | | | | | | Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
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| * | / | | | | | | | | | | | | | | | | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
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| * | | | | | | | | | | | | | | | | | | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| * | | | | | | | | | | | | | | | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-074-3/+42
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| | * | | | | | | | | | | | | | | | | | | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
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* | | | | | | | | | | | | | | | | | | | Add nonexcl case test, comment out two othersEddie Hung2019-06-072-22/+57
* | | | | | | | | | | | | | | | | | | | Add @cliffordwolf freduce testcaseEddie Hung2019-06-072-0/+30
* | | | | | | | | | | | | | | | | | | | Add nonexclusive test from @cliffordwolfEddie Hung2019-06-072-0/+28
* | | | | | | | | | | | | | | | | | | | Another muxpack testEddie Hung2019-06-072-0/+32
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* | | | | | | | | | | | | | | | | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
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* | | | | | | | | | | | | | | | | | Fix warningsEddie Hung2019-06-062-3/+3
* | | | | | | | | | | | | | | | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
* | | | | | | | | | | | | | | | | | Add non exclusive testEddie Hung2019-06-062-0/+56