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authorEddie Hung <eddie@fpgeh.com>2019-06-06 14:21:34 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-06 14:21:34 -0700
commit5c277c6325b78bfe18cf294b63ea69ff272e69c5 (patch)
tree5407195159a09be5b3fd7f8af0e7d28dee7c6f75 /tests
parent0a66720f6f67b087fe6342d01d45944506240942 (diff)
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Fix and test for balanced case
Diffstat (limited to 'tests')
-rw-r--r--tests/various/muxpack.v26
-rw-r--r--tests/various/muxpack.ys15
2 files changed, 41 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7c189fff8..f1bd5ea8e 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,3 +110,29 @@ always @* begin
endcase
end
endmodule
+
+module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+ if (s[0] == 1'b0)
+ if (s[1] == 1'b0)
+ if (s[2] == 1'b0)
+ o <= i[0*W+:W];
+ else
+ o <= i[1*W+:W];
+ else
+ if (s[2] == 1'b0)
+ o <= i[2*W+:W];
+ else
+ o <= i[3*W+:W];
+ else
+ if (s[1] == 1'b0)
+ if (s[2] == 1'b0)
+ o <= i[4*W+:W];
+ else
+ o <= i[5*W+:W];
+ else
+ if (s[2] == 1'b0)
+ o <= i[6*W+:W];
+ else
+ o <= i[7*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 0c5b82818..9ea743b9f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,3 +133,18 @@ design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_8_2
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 7 t:$mux
+select -assert-count 0 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter