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* Add unconditional match blocks for force RAMEddie Hung2019-12-161-0/+9
* Merge blockram testsEddie Hung2019-12-163-47/+81
* Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-6/+6
* Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-3238/+0
* Merging attribute rules into a single match block; Adding testsDiego H2019-12-153-0/+3373
* Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
* Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-2/+2
* Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
* Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-122-0/+90
* Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-093-23/+136
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| * unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
| * ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-3/+5
| * Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-2/+2
| * Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
| * Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
| * Add testcaseEddie Hung2019-12-031-0/+60
* | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
* | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-0/+99
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* Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-033-2/+301
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| * update testPepijn de Vos2019-12-031-2/+3
| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-10/+12
| * attempt to fix formattingPepijn de Vos2019-11-251-138/+138
| * gowin: add and test dff init valuesPepijn de Vos2019-11-252-0/+296
* | abc9: Fix breaking of SCCsDavid Shah2019-12-011-0/+6
* | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-271-0/+69
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| * | No need for -abc9Eddie Hung2019-11-261-1/+1
| * | Add citationEddie Hung2019-11-261-0/+1
| * | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
* | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-271-0/+13
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| * | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-271-0/+13
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* / / Remove notesEddie Hung2019-11-261-9/+0
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* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-5/+16
* | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-254-8/+8
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* Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-221-0/+63
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| * sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
* | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1912-0/+248
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| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-165-17/+34
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-0/+11
| * | fix wide lutsPepijn de Vos2019-11-061-7/+10
| * | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| * | add tristate buffer and testPepijn de Vos2019-10-281-0/+13
| * | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| * | ALU sim tweaksPepijn de Vos2019-10-241-2/+2
| * | Add some testsPepijn de Vos2019-10-2110-0/+224
* | | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-0/+29
* | | Fix #1496.Marcin Kościelnicki2019-11-181-0/+13
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* | Fixed testsMiodrag Milanovic2019-11-115-17/+34
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* fixed errorMiodrag Milanovic2019-10-181-1/+1
* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
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