diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:15 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:31:15 -0800 |
| commit | 5a00d5578cea91ce84f3d95e6138c85d1a949b89 (patch) | |
| tree | 6734b8efe4366ebccc958c302984aa2be9d5601a /tests | |
| parent | 6b384861e4b1e02b24bf11d266cf11f461115cd8 (diff) | |
| download | yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.tar.gz yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.tar.bz2 yosys-5a00d5578cea91ce84f3d95e6138c85d1a949b89.zip | |
Add unconditional match blocks for force RAM
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 362d33229..b6e105854 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 |