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* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2110-5/+225
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| * Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
| |\ | | | | | | Add specify parser
| | * Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * More testingEddie Hung2019-05-032-2/+5
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| | * Fix spacingEddie Hung2019-05-031-6/+6
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| | * Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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| * | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
| |\ \ | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| | * | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
| |\ \ \ | | |_|/ | |/| | Improve verific -chparam and add hierarchy -chparam
| | * | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
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| * | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
| |\ \ \ | | |/ / | |/| | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| * | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
| |\ \ \ | | | | | | | | | | Fix width detection of memory access with bit slice
| | * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
| | | |/ | | |/| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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* | | | Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7muxEddie Hung2019-05-021-0/+9
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| * | | Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-022-0/+23
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| * | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-012-0/+23
| |/ | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* | Remove split_shiftx testsEddie Hung2019-04-262-139/+0
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* | Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7muxEddie Hung2019-04-252-0/+139
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| * | Add testEddie Hung2019-04-252-0/+139
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* | Remove topo sort no-loop assertion, with testEddie Hung2019-04-243-1/+76
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* | Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-0/+38
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-224-0/+110
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| * Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #909 from zachjs/masterClifford Wolf2019-04-222-0/+48
| |\ | | | | | | support repeat loops with constant repeat counts outside of constant functions
| | * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
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| * | Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
| |\ \ | | | | | | | | Add pmux2shiftx command
| | * | Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/clifford/libwb' into xaigEddie Hung2019-04-212-2/+3
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| * | | Fix testsClifford Wolf2019-04-212-2/+3
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-0/+8
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| * | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add retime testEddie Hung2019-04-051-0/+6
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* | Select to find union of both sets on stackEddie Hung2019-04-191-1/+1
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* | Re-enable partsel.v testEddie Hung2019-04-161-1/+0
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-151-3/+2
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| * | Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-151-3/+2
| | | | | | | | | | | | #931)"
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-121-2/+3
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| * | Add default entry to testcaseEddie Hung2019-04-111-2/+3
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* | Merge branch 'master' into xaigEddie Hung2019-04-0814-5/+737
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| * Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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