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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:49:18 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:49:18 -0700 |
commit | 42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae (patch) | |
tree | 7424614f63ebff3d26712b8f9d947f68f6411d9e /tests | |
parent | caec7f9d2c87e3978c51d0a4171b24cc4b363885 (diff) | |
parent | d38f0c1a96c036df4ef67ad2f945dd229e1c3b8e (diff) | |
download | yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.tar.gz yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.tar.bz2 yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.zip |
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
Diffstat (limited to 'tests')
-rwxr-xr-x | tests/tools/autotest.sh | 4 | ||||
-rw-r--r-- | tests/various/hierarchy.sh | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 99768b0ec..86a90793e 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -7,7 +7,7 @@ use_modelsim=false verbose=false keeprunning=false makejmode=false -frontend="verilog" +frontend="verilog -noblackbox" backend_opts="-noattr -noexpr -siminit" autotb_opts="" include_opts="" @@ -136,7 +136,7 @@ do egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog" + frontend="verilog -noblackbox" fi rm -f ${bn}_ref.fir diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh index d33a247be..9dbd1c89f 100644 --- a/tests/various/hierarchy.sh +++ b/tests/various/hierarchy.sh @@ -53,6 +53,7 @@ echo -n " no explicit top - " module noTop(a, y); input a; output [31:0] y; + assign y = a; endmodule EOV hierarchy -auto-top |