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* Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-101-1/+6
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| * Add some more commentsEddie Hung2019-06-101-1/+6
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* | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-0728-33/+138
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| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
| |\ | | | | | | elaboration system tasks
| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
| | |\ | | | | | | | | | | | | clifford/pr983
| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-074-3/+42
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | | Add nonexcl case test, comment out two othersEddie Hung2019-06-072-22/+57
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* | | | Add @cliffordwolf freduce testcaseEddie Hung2019-06-072-0/+30
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* | | | Add nonexclusive test from @cliffordwolfEddie Hung2019-06-072-0/+28
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* | | | Another muxpack testEddie Hung2019-06-072-0/+32
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* | | | Fix and test for balanced caseEddie Hung2019-06-062-0/+41
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* | | | Fix warningsEddie Hung2019-06-062-3/+3
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* | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
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* | | | Add non exclusive testEddie Hung2019-06-062-0/+56
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* | | | One more and tidy upEddie Hung2019-06-062-6/+28
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* | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
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* | | | Add tests, fix for !=Eddie Hung2019-06-062-0/+78
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* | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
|\ \ | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| * | Fix initEddie Hung2019-05-241-27/+27
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| * | Fix typosEddie Hung2019-05-241-6/+6
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| * | Add more testsEddie Hung2019-05-242-20/+41
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| * | Call procEddie Hung2019-05-241-1/+1
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| * | Fix duplicate driverEddie Hung2019-05-241-15/+15
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| * | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
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* | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
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* | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
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* | Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
|\ \ | | | | | | Add specify parser
| * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | More testingEddie Hung2019-05-032-2/+5
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| * | Fix spacingEddie Hung2019-05-031-6/+6
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| * | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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* | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
|\ \ \ | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| * | | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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