aboutsummaryrefslogtreecommitdiffstats
path: root/tests/various
Commit message (Collapse)AuthorAgeFilesLines
* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-191-0/+33
| | | | Fixes #1781.
* Add test for `exec` command.Alberto Gonzalez2020-03-161-0/+6
|
* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-0/+24
|\ | | | | refixed parsing of constant with comment between size and value
| * Add regression tests for new handling of comments in constantsMarcus Comstedt2020-03-142-0/+24
| |
* | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-0/+8
|\ \ | | | | | | Set AST node source location in more parser rules.
| * | verilog: add testEddie Hung2020-03-111-0/+8
| | |
* | | Added back tests for loggerMiodrag Milanovic2020-03-134-0/+24
| |/ |/|
* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-0/+14
|\ \ | |/ |/| deminout: Don't demote inouts with unused bits
| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-0/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+2
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| |/ | | | | | | line number.
* | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-0/+124
|\ \ | | | | | | submod: several bugfixes
| * \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-017-11/+98
| |\ \
| * | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
| | | |
* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-19/+1
|\ \ \ \ | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | Cleanup testsEddie Hung2020-02-272-19/+1
| | |_|/ | |/| |
* / | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-0/+30
|/ / /
* | | clean: ignore specify-s inside cells when determining whether to keepEddie Hung2020-02-191-1/+20
| | |
* | | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-0/+7
| | |
* | | verilog: improve specify support when not in -specify modeEddie Hung2020-02-132-3/+1
| | |
* | | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-0/+6
| | |
* | | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-0/+7
| | |
* | | verilog: fix $specify3 checkEddie Hung2020-02-131-0/+7
| | |
* | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-0/+5
|\ \ \ | | | | | | | | Fix crash on wire declaration with delay
| * | | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
| | |/ | |/|
* | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-0/+11
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | sv: Add tests for wildcard port connectionsDavid Shah2020-02-021-0/+56
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-021-0/+12
|\ \ \ | |/ / |/| | ast: Add support for $sformatf system function
| * | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
| | |
* | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-211-11/+0
|\| |
| * | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-11/+0
| | |
* | | write_xaiger: fix for (* keep *) on flop outputEddie Hung2020-01-211-0/+15
|/ /
* | autoname: add testcase with $-prefix-ed portEddie Hung2020-01-141-0/+19
| |
* | Remove submod changesEddie Hung2019-12-301-102/+0
| |
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-0/+34
|\ \
| * \ Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-191-0/+34
| |\ \ | | | | | | | | verilog: preserve size of $genval$-s in for loops
| | * | Add testcaseEddie Hung2019-12-111-0/+34
| | | |
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-0/+5
|\| | |
| * | | add assert option to scratchpad commandN. Engelhardt2019-12-162-14/+5
| | | |
| * | | add test and make help message more verboseN. Engelhardt2019-12-121-0/+14
| |/ /
* | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-0/+31
|\ \ \ | | |/ | |/|
| * | Add multiple driver testcaseEddie Hung2019-11-271-0/+31
| | |
* | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-2/+23
|\| |
| * | Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-271-2/+5
| | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
| * | Fix wire widthEddie Hung2019-11-261-2/+2
| | |
| * | Add testcase where \init is copiedEddie Hung2019-11-251-0/+18
| | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 04:30:27 +0000