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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 09:43:04 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 09:43:04 -0800 |
| commit | cd8f55a91100b8dcf8b4775803cbacf70f5a998c (patch) | |
| tree | 6ad1a8856d8c2292c76abd60781df682c19cc296 /tests/various | |
| parent | d4e188299ba729756ee689d14c81aab68a7ca1b7 (diff) | |
| download | yosys-cd8f55a91100b8dcf8b4775803cbacf70f5a998c.tar.gz yosys-cd8f55a91100b8dcf8b4775803cbacf70f5a998c.tar.bz2 yosys-cd8f55a91100b8dcf8b4775803cbacf70f5a998c.zip | |
write_xaiger: fix for (* keep *) on flop output
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/abc9.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 81d0afd1b..0c7695089 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -14,6 +14,7 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + design -load read hierarchy -top abc9_test028 proc @@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D + design -load read hierarchy -top abc9_test032 proc @@ -38,3 +40,16 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -seq 10 -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells <<EOT +module abc9_test036(input clk, d, output q); +(* keep *) reg w; +$__ABC9_FF_ ff(.D(d), .Q(w)); +wire \ff.clock = clk; +wire \ff.init = 1'b0; +assign q = w; +endmodule +EOT +abc9 -lut 4 -dff |