| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Fix in sincos testbench gen | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Added sincos test case | Clifford Wolf | 2013-12-04 | 1 | -0/+124 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 1 | -1/+7 |
| * | Added modelsim support to autotest | Clifford Wolf | 2013-11-24 | 1 | -0/+21 |
| * | Another name resolution bugfix for generate blocks | Clifford Wolf | 2013-11-20 | 1 | -0/+48 |
| * | Implemented indexed part selects | Clifford Wolf | 2013-11-20 | 1 | -0/+5 |
| * | Implemented part/bit select on memory read | Clifford Wolf | 2013-11-20 | 1 | -0/+41 |
| * | Added additional mem2reg testcase | Clifford Wolf | 2013-11-18 | 1 | -0/+28 |
| * | Fixed parsing of default cases when not last case | Clifford Wolf | 2013-11-18 | 1 | -0/+22 |
| * | Fixed handling of power operator | Clifford Wolf | 2013-11-07 | 1 | -0/+15 |
| * | Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before... | Clifford Wolf | 2013-11-02 | 1 | -6/+6 |
| * | Various ast changes for early expression width detection (prep for constfold ... | Clifford Wolf | 2013-11-02 | 1 | -0/+7 |
| * | Added support for complex set-reset flip-flops in proc_dff | Clifford Wolf | 2013-10-24 | 1 | -12/+26 |
| * | Improved handling of dff with async resets | Clifford Wolf | 2013-10-21 | 1 | -0/+39 |
| * | Added support for "2**n" shifter encoding | Clifford Wolf | 2013-08-12 | 1 | -24/+29 |
| * | Added $div and $mod technology mapping | Clifford Wolf | 2013-08-09 | 1 | -21/+40 |
| * | More fixes in ternary op sign handling | Clifford Wolf | 2013-07-12 | 1 | -0/+8 |
| * | Fixed sign handling in ternary operator | Clifford Wolf | 2013-07-12 | 1 | -0/+8 |
| * | Another vloghammer related bugfix | Clifford Wolf | 2013-07-11 | 1 | -0/+7 |
| * | More fixes in ast expression sign/width handling | Clifford Wolf | 2013-07-09 | 1 | -13/+15 |
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2013-07-09 | 1 | -0/+18 |
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| | * | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 | 1 | -0/+18 |
| * | | Fixed shift ops with large right hand side | Clifford Wolf | 2013-07-09 | 1 | -3/+43 |
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| * | Fixed another bug found using vloghammer | Clifford Wolf | 2013-07-07 | 1 | -0/+10 |
| * | Added defparam support to Verilog/AST frontend | Clifford Wolf | 2013-07-04 | 1 | -0/+16 |
| * | Fixed a bug in AST frontend for cases with non-blocking assigned variables as... | Clifford Wolf | 2013-04-13 | 1 | -0/+19 |
| * | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | Clifford Wolf | 2013-03-31 | 6 | -0/+111 |
| * | Renamed hansimem.v test case to mem_arst.v | Clifford Wolf | 2013-03-24 | 1 | -1/+0 |
| * | Added hansimem testcase (memory with async reset) | Clifford Wolf | 2013-03-24 | 1 | -0/+44 |
| * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 | 1 | -0/+7 |
| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 | 1 | -0/+2 |
| * | initial import | Clifford Wolf | 2013-01-05 | 19 | -0/+905 |
