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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-09 19:00:10 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-09 19:00:10 +0200 |
| commit | 618b2ac994360de4ffc9299aecb104a5bf5ba721 (patch) | |
| tree | eab20d78333bf2d266bb3d6b62738299f871525b /tests/simple | |
| parent | 7daeee340a7edad3f4450e1392f8bad8d8b9cb7c (diff) | |
| parent | 00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd (diff) | |
| download | yosys-618b2ac994360de4ffc9299aecb104a5bf5ba721.tar.gz yosys-618b2ac994360de4ffc9299aecb104a5bf5ba721.tar.bz2 yosys-618b2ac994360de4ffc9299aecb104a5bf5ba721.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/signedexpr.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v new file mode 100644 index 000000000..3eb5e93df --- /dev/null +++ b/tests/simple/signedexpr.v @@ -0,0 +1,18 @@ +module test01(a, b, xu, xs, yu, ys, zu, zs); + +input signed [1:0] a; +input signed [2:0] b; +output [3:0] xu, xs; +output [3:0] yu, ys; +output zu, zs; + +assign xu = (a + b) + 3'd0; +assign xs = (a + b) + 3'sd0; + +assign yu = {a + b} + 3'd0; +assign ys = {a + b} + 3'sd0; + +assign zu = a + b != 3'd0; +assign zs = a + b != 3'sd0; + +endmodule |