iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	Moved all tests in arch sub directory	Miodrag Milanovic	2019-10-18	1	-41/+0
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*	hierarchy - proc reorder	Miodrag Milanovic	2019-10-18	1	-4/+4
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*	Split mux tests per type	Miodrag Milanovic	2019-10-04	1	-3/+36
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*	Add new tests for Efinix architecture.	SergeyDegtyar	2019-09-23	1	-0/+8
	Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.